CHAPTER
12
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SCC
y
SMC1: Debugging port to be used for engineers
Clock
y
The CPU clock uses 50 MHz as the main clock oscillator.
y
The synchronization of the system clock is performed by the PLL circuit of a MP40
board.
y
4.096 MHz, 8.192 MHz, FOI and FSX are supplied by the mother board.
y
4.096 MHz of the mother board is supplied to SCLKX/SCLKR of PEF2256H.
y
The active signal displaying the Valid Reference clock is received in the CPU port.
Boot ROM
(
Flash ROM)
y
512 Kbytes flash ROM(SST39VF040) is used for the Boot ROM.
y
The Boot ROM uses a socket and stores the boot program and DB information.
Application ROM (Flash ROM)
y
Application ROM uses 4 Mbytes flash ROM(AM29LV320D).
y
Application ROM is used as and stores application programs.
SDRAM
y
SDRAM uses 16 Mbytes DRAM(K4S641632) and consists of two 8 Mbytes elements.
y
The main program resides in the SDRAM and the SDRAM stores the data for the system
processing. The RAM backup is not required.
y
The access time to SDRAM is set as short as possible for the maximum system
performance.
WATCH DOG
y
WATCH DOG is the function that recovers the system when a board is malfunction.
It restarts when it operates abnormally for five seconds.
LAN Interface
y
LAN access is available with no additional LAN board.
y
CPU embeds the 10/100 PHY MAC address.
y
The maximum access speed is 100 Mbps.
y
When the system is connected to LAN, the system detects the speed automatically
(Auto Nego).
y
Remote Monitoring function via Ethernet
y
PHY uses LXT972 and operates in 10/100 Mbps Full Duplex
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