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Using PEEDI
Example for SPI memory connected to a Blackfin CPU:
http://download.ronetix.at/peedi/cfg_examples/blackfin/bf532.cfg
Example for SPI memory connected to a NXP LPC2000 CPU:
http://download.ronetix.at/peedi/cfg_examples/arm7/lpc2468.cfg
Example for SPI memory connected to a NXP LPC4000 CPU:
http://download.ronetix.at/peedi/cfg_examples/cortex-m/lpc4300.cfg
PEEDI also supports software emulated SPI interface FLASH programming. In this case the
FLASH is connected to CPU GPIOs and PEEDI drives them to emulate SPI interface. Here are the
needed configuration parameters:
CHIP
CPU
CS_ASSERT/RELEASE,
SCLK_SET/CLR, MOSI_SET/CLR,
MISO_READ
FILE
AUTO_ERASE
Example:
http://download.ronetix.at/peedi/cfg_examples/arm9/at91sam9263_soft_spi.cfg
NAND FLASH programming
PEEDI is able to program all NAND chips with 8 and 16 bits data bus.
The INIT section of the config file must include the initialization for the chip select and the GPIOs,
because the Flash Programmer doesn't make any initialization. The NAND Flash devices may have
blocks that are invalid when they are shipped. An invalid block is one that contains one or more bad
bits. Additional bad blocks may develop with use. The factory identifies invalid blocks before
shipping by programming data other than FFh (x8) or FFFFh (x16) into the first spare location of
the first or second page of each bad block. PEEDI automatically detects the bad blocks and reports
them using the
flash info
and
flash query
commands.
PEEDI User’s Manual
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