Using PEEDI
configure and control the caches, MMU, protection system, the clocking mode and
other system options.
Via JTAG, CP15 registers are accessed either direct (physical access mode) or via
interpreted MCR/MRC instructions.
ARM920: Physical and Interpreted access mapping to CP15 registers Register number
for physical access mode (bit 12 = 0):
15 13
12
11 9
8
7 5
4
3 0
0 0 0
0
0 0
i
0 0 0
x
CRn
The bit "i" selects the instruction cache (scan chain bit 33)
The bit "x" extends access to register 15 (scan chain bit 38)
Register number for interpreted access mode (bit 12 = 1):
15 13
12
11 8
7 5
4
3 0
opc_2
1
CRm
opc_2
x
CRn
The 16-bit register number is used to build the appropriate MCR/MRC instruction.
•
CRm - Specified Coprocessor Action. Determines specific coprocessor action.
Its value is dependent on the CP15 register used. For details, refer to CP15
specific register behavior.
•
CRn - Determines the destination coprocessor register.
•
opc_1 - Defines the coprocessor specific code. Value is c15 for CP15.
•
opc_2 - Determines specific coprocessor operation code. By default, set to 0.
ARM926
: Physical access mapping to CP15 registers:
13 11
10 8
7 4
3 0
opc_1
opc_2
CRn
CRm
ARM94x
: Physical access mapping to CP15 registers:
5
4 1
0
x
CRn
i
PEEDI User’s Manual
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