Using PEEDI
Description:
Software breakpoint pattern.
Since Firmware v20.12.xx this parameter is obsolete.
Section PLATFORM_Cortex & Section PLATFORM_Cortex_SWD
These sections describe the Cortex-A and Cortex-M cores connected to PEEDI via JTAG or SWD
(Serial Wire Debug).It has all the parameters described in the PLATFORM_ARM section (except
the
COREn_VECTOR_CATCH_MASK,
and
COREn_DCC_PORT.
The
PLATFORM_Cortex_SWD section has no JTAG_CHAIN parameter, and its clock parameter is
named SWD_CLOCK and has the same format as the JTAG_CLOCK parameter. About the CORE
parameter:
COREn
Synopsis:
COREn = Cortex-M|Cortex-A|Cortex-ARMv8 [tap_num] [tap_id]
COREn = Cortex-A_SMP
COREn = Cortex-A_AMP
Description:
The detection of Cortex-A and Cortex-M variants is done automatically. value. Suffix
’_SMP’ defines cores in a SMP group. Suffix ’_AMP’ defines cores in a AMP group.
All cores in a SMP group start, halt, break and single step simultaneously. All cores in a
AMP group can be set to start, halt, break and single step simultaneously or not. This
can be set with the ’amp’ command.
Example:
CORE0 = Cortex-A, 0
CORE0 = Cortex-ARMv8, 0
CORE0 = Cortex-M, 1, 0xBC11477
COREn_APSEL
Synopsis:
COREn_APSEL = 0 .. 255
PEEDI User’s Manual
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