RME Audio Digiface AES, Руководство пользователя

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User's Guide Digiface AES
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38.6 SteadyClock FS
RME’s SteadyClock technology guarantees an excellent performance in all clock modes. Its
highly efficient jitter suppression refreshes and cleans up any clock signal. Thanks to the efficient
jitter suppression, the AD- and DA-conversion always operates on highest sonic level, being com-
pletely independent from the quality of the incoming clock signal.
RME realizes modern circuit designs like hi-speed digital synthesizer, digital PLL and 800 MHz
sample rate cost- and space-saving right within the FPGA. Combined with analog and digital
filtering a professional clock technology is created that is second to none. Also SteadyClock reacts
quite fast compared to other techniques. It locks in fractions of a second to the input signal, follows
even extreme varipitch changes with phase accuracy, and locks directly within a range of 28 kHz
up to 200 kHz.
The analysis of so-called
interface jitter
with the help of an oscilloscope shows
how it works. The screenshot shows a
very jittery SPDIF signal with about 50
ns jitter (top graph, yellow). Steady-
Clock turns this signal into a clean clock
signal with less than 2 ns jitter (lower
graph, blue). The signal processed by
SteadyClock is not only used internally,
but also used to clock the digital out-
puts. Therefore the refreshed and jitter-
cleaned signal can be used as refer-
ence clock without hesitation.
The so-called
sampling jitter , usually in the range of picoseconds, is also very low in the Digiface
AES. One way to show this is to send out a specially modulated 11.025 kHz sine from the analog
output, then analyze the sampled result. Jitter products are shown in the measurement as sym-
metrical sidebands, like narrow needles. SteadyClock does not show obvious sidebands. Also
remarkable is the identical performance when using internal or external clock
– a typical Steady-
Clock feature. Check RM
E’s YouTube channel for a video showing and explaining such meas-
urements.
The further improved Steady-
Clock FS technology attenuates
even lowest frequency jitter (>1
Hz), and provides an even
higher jitter suppression at low-
est self-jitter. Of course, this can
also be proven by measure-
ment. In this measurement, an
AES signal with 0 ns (refer-
ence), 100 ns and 400 ns (!) jit-
ter is applied, and the modula-
tion frequency is swept in the
range 20 Hz to 20 kHz in each
case. At 50 Hz, approximately
210 ps can be detected, corre-
sponding to a jitter suppression
of > 65 dB. This is simply fantas-
tic for such low frequencies.