Rev. 1.50, 10/04, page 139 of 448
7.4.4
Hardware ITLB Miss Handling
In an instruction access, the SH-4A searches the ITLB. If it cannot find the necessary address
translation information (ITLB miss occurred), the UTLB is searched by hardware, and if the
necessary address translation information is present, it is recorded in the ITLB. This procedure is
known as hardware ITLB miss handling. If the necessary address translation information is not
found in the UTLB search, an instruction TLB miss exception is generated and processing passes
to software.
7.4.5
Avoiding Synonym Problems
When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The
problem is that, when a number of virtual addresses are mapped onto a single physical address, the
same physical address data is recorded in a number of cache entries, and it becomes impossible to
guarantee data integrity. This problem does not occur with the instruction TLB and instruction
cache because data is only read in these cases. In this LSI, entry specification is performed using
bits 12 to 5 of the virtual address in order to achieve fast operand cache operation. However, bits
12 to 10 of the virtual address in the case of a 1-Kbyte page, and bit 12 of the virtual address in the
case of a 4-Kbyte page, are subject to address translation. As a result, bits 12 to 10 of the physical
address after translation may differ from bits 12 to 10 of the virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in UTLB entries.
•
When address translation information whereby a number of 1-Kbyte page UTLB entries are
translated into the same physical address is recorded in the UTLB, ensure that the VPN[12:10]
values are the same.
•
When address translation information whereby a number of 4-Kbyte page UTLB entries are
translated into the same physical address is recorded in the UTLB, ensure that the VPN[12]
value is the same.
•
Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different
page size.
•
Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different
page size.
The above restrictions apply only when performing accesses using the cache.
Note: When multiple items of address translation information use the same physical memory to
provide for future expansion of the SuperH RISC engine family, ensure that the
VPN[20:10] values are the same. Also, do not use the same physical address for address
translation information of different page sizes.
Содержание SuperH SH-4A
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