RX Family
ADC Module Using Firmware Integration Technology
R01AN1666EJ0220 Rev. 2.20
Page 50 of 74
Dec 01, 2016
ADC_REG_CH0 =
0
,
ADC_REG_CH1 =
1
,
ADC_REG_CH2 =
2
,
ADC_REG_CH3 =
3
,
ADC_REG_CH4 =
4
,
ADC_REG_CH5 =
5
,
ADC_REG_CH6 =
6
,
ADC_REG_CH7 =
7
,
// last channel unit0
ADC_REG_CH8 =
8
,
ADC_REG_CH9 =
9
,
ADC_REG_CH10 =
10
,
ADC_REG_CH11 =
11
,
ADC_REG_CH12 =
12
,
ADC_REG_CH13 =
13
,
ADC_REG_CH14 =
14
,
ADC_REG_CH15 =
15
,
ADC_REG_CH16 =
16
,
ADC_REG_CH17 =
17
,
ADC_REG_CH18 =
18
,
ADC_REG_CH19 =
19
,
ADC_REG_CH20 =
20
,
ADC_REG_TEMP,
ADC_REG_VOLT,
// both units
ADC_REG_DBLTRIG,
ADC_REG_DBLTRIGA,
// loaded when first multi-source trigger was A
ADC_REG_DBLTRIGB,
// loaded when first multi-source trigger was B
ADC_REG_SELF_DIAG,
ADC_REG_MAX
}
adc_reg_t;
#define
ADC_0_REG_ARRAY_MAX (
8
)
#define
ADC_1_REG_ARRAY_MAX (
21
)
/* ADC_READALL() ARGUMENT DEFINITIONS */
typedef
struct
st_adc_unit0_data
{
uint16_t chan
[
ADC_0_REG_ARRAY_MAX
]
;
uint16_t dbltrig;
uint16_t dbltrigA;
uint16_t dbltrigB;
uint16_t self_diag;
}
adc_unit0_data_t;
typedef
struct
st_adc_unit1_data
{
uint16_t chan
[
ADC_1_REG_ARRAY_MAX
]
;
uint16_t temp;
uint16_t volt;
uint16_t dbltrig;
uint16_t dbltrigA;
uint16_t dbltrigB;
uint16_t self_diag;
}
adc_unit1_data_t;
typedef
struct
st_adc_data
{
adc_unit0_data_t unit0;
adc_unit1_data_t unit1;
}
adc_data_t;