RX Family
ADC Module Using Firmware Integration Technology
R01AN1666EJ0220 Rev. 2.20
Page 43 of 74
Dec 01, 2016
#define
ADC_SST_SH_CNT_DEFAULT (
24
)
// default sample&hold states
typedef
struct
st_adc_ch_cfg
// bit 0 is ch0; bit 15 is ch15
{
uint32_t scan_mask;
// channels/bits 0-15
uint32_t scan_mask_groupb;
// valid for group modes
adc_grpa_t priority_groupa;
// valid for group modes
uint32_t add_mask;
// valid if add enabled in Open()
adc_diag_t diag_method;
// self-diagnosis virtual channel
bool
anex_enable;
// unit1: use external amplifier
uint8_t sample_hold_mask;
// channels/bits 0-2
uint8_t sample_hold_states;
// minimum .4us
}
adc_ch_cfg_t;
/* for ADC_CMD_EN_COMPARATOR_LEVEL and ADC_CMD_EN_COMPARATOR_WINDOW */
typedef
struct
st_adc_cmpwin_cfg
// bit-OR ADC_MASK_xxx to
{
// indicate channels/sensors
uint32_t compare_mask;
// channels/sensors to compare
uint32_t inside_window_mask;
// condition met when within range
// default=0 met when outside range
uint16_t level_lo;
uint16_t level_hi;
uint8_t int_priority;
// S12CMPI priority level
// 1=low 15=hi 0=polled
}
adc_cmpwin_t;
/***** ADC_READ() ARGUMENT DEFINITIONS *****/
typedef
enum
e_adc_reg
{
ADC_REG_CH0 =
0
,
ADC_REG_CH1 =
1
,
ADC_REG_CH2 =
2
,
ADC_REG_CH3 =
3
,
ADC_REG_CH4 =
4
,
ADC_REG_CH5 =
5
,
ADC_REG_CH6 =
6
,
ADC_REG_CH7 =
7
,
// last channel unit0
ADC_REG_CH8 =
8
,
ADC_REG_CH9 =
9
,
ADC_REG_CH10 =
10
,
ADC_REG_CH11 =
11
,
ADC_REG_CH12 =
12
,
ADC_REG_CH13 =
13
,
ADC_REG_CH14 =
14
,
ADC_REG_CH15 =
15
,
ADC_REG_CH16 =
16
,
ADC_REG_CH17 =
17
,
ADC_REG_CH18 =
18
,
ADC_REG_CH19 =
19
,
ADC_REG_CH20 =
20
,
ADC_REG_TEMP,
ADC_REG_VOLT,
// both units
ADC_REG_DBLTRIG,
ADC_REG_DBLTRIGA,
// loaded when first multi-source trigger was A
ADC_REG_DBLTRIGB,
// loaded when first multi-source trigger was B
ADC_REG_SELF_DIAG,