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EPC-7 Hardware Reference
Read-Modify-Write Operations
The EPC-7 provides synchronization integrity in its local DRAM between accesses
from the 486 into the DRAM and RMW VXI accesses from other masters into the
DRAM.
When a VXIbus slave read access occurs to the local DRAM, the EPC-7 watches the
VXIbus data and address strobes to determine if the cycle is an RMW cycle. If it is,
accesses by the 486 are held up until the terminating access of the RMW cycle
occurs.
When the 486 performs a locked access (e.g., via an instruction using the LOCK
instruction prefix) to the local DRAM, VXIbus accesses are held up until the last
locked access completes.
One more case of interest is when the EPC-7 performs a locked access that results in
a self access. These function correctly (i.e., as if the access were not a self access),
providing that operating-system tables (e.g., page tables) that are accessed by the 486
by implicit locked accesses are not mapped into VXI. This would only be a concern
for user-written operating systems.
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VXIbus RMW (read-modify-write) cycles can be performed through use of the 486's
LOCK instruction prefix with certain instructions. All of these instructions perform a
read followed by a write. When such a read occurs that is mapped to the VXIbus, the
EPC-7 treats it as the start of a VXI RMW cycle. The next VME access from the 486
is treated as the write that terminates the RMW cycle. For this reason, RMW
accesses that cross a 32-bit boundary will not behave as expected (because the 486
issues two read accesses).
Soft Reset and VME Sysreset
The EPC-7 supports two device states specified by the VXI: soft reset and safe. These
states are identical except that, in the safe state, the EPC-7 cannot drive SYSFAIL.
The soft reset state is entered by setting bit RSTP. Setting bit NOSF when FSTP is set
denotes the safe state.
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