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EPC-7 Hardware Reference
One more case of interest is when the EPC-7 performs a locked access that results in
a self access. These function correctly (i.e., as if the access was not a self access),
providing that operating-system tables (e.g., page tables) that are accessed by the
CPU by implicit locked accesses are not mapped into VME. This would only be a
concern for user-written operating systems.
VMEbus Interrupt Response
When the EPC-7's Interrupt Generator register (815F) is used to assert an interrupt,
the EPC-7 formulates a status/ID value that is transmitted on the bus as the response
to a matching interrupt acknowledge cycle. The EPC-7 acts as both a D08(O) and
D16 interrupter. For D08 interrupt acknowledge cycles, the status/ID value is the
contents of register 815C. For D16 and D32 interrupt acknowledge cycles, the
status/ID value consists of 16 bits. The upper eight bits are the upper half of the
response register (the value in I/O port 814B) and the lower eight bits are the contents
of register 815C.
Registers Specific to EPC-7
Registers in the I/O space that are specific to the EPC-7 are defined below.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I/O
port
EXM Configuration Reg reserved Slot Number 96
7 7
Battery Backed Register ARBPRI
RELM ARBM RAM SDMA EVME 0
8102
Memory Mode Register
MDFF MDCF
RAM MEMS RAM RAM 8104
VME A21-16 Address Reg VMEbus address bits 21-16 RAM RAM 8130
ID Register, lower 1 1 1 0 1 1 0 0 8140
ID Register, upper 1 0 0 A32 1 1 1 1 8141
Device Type Reg, lower 1 1 1 0 1 1 1 1 8142
Device Type Reg, upper 0 Slave Size 1 0 0 0 S 8143
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