
Theory of Operation
Processor and Memory
The processor is a derivative of the Intel 80486 DX. The EPC-7 was designed to
work with a variety of models and frequencies of 486s; the ordering information will
identify the exact 486 used. The EPC-7 is shipped as either a 33 MHz 486DX, a 50
MHz 486 DX or a 100 MHz 486 DX4. The 33 Mhz and 50 MHz EPC-7s contain an
integrated floating-point coprocessor and 8 KB cache; the 100 MHz EPC-7 contains
an integrated floating-point coprocessor and a 16 KB cache.
The processor board contains four 72-pin SIMM sockets. The factory-installed
DRAM options are 2, 4, 8, 16, 32, or 64 MB. The DRAM has byte-wide parity. The
50 MHz EPC-7 does not support 4 MBytes of DRAM. The 33 MHz EPC-7 does not
support 64 MBytes of DRAM. 100 MHz EPC-7s come with either 8, 16, 32, or 64
MB of DRAM.
Cached and Uncached Addresses
5
5
The 486 in the EPC-7 contains a cache. The cache is designed to cache selectively by
address range, because many memory areas defined by the PC architecture, as well as
memory mapped to the VXIbus and potentially some mapped to the EXM expansion
interface, cannot be safely cached. What
is
cached is the first 640 KB of memory
and all DRAM above 1 MB, meaning the following address ranges:
0000 0000 to 0009 FFFF
0010 0000 to 03FF FFFF
The use of a cache with dual-port memory (i.e., DRAM in the EPC-7 that is also
accessible by other VXIbus masters) raises the issue of "stale data." This is prevented
by the "bus watching" logic of the cache controller. Any write into the EPC-7's
DRAM from another VXI master will cause the data at these addresses, if it happens
to be in the cache, to be invalidated in the cache, meaning that a subsequent read of
the data from the 486 will fetch the updated value from DRAM.
ROM and ROM Shadowing
EPC-7 contains a 27010 1 MB EPROM. The EPROM is mapped into the top of the
processor's 32-bit address space, and also just below the 16 MB boundary for PC/AT
compatibility. The EPROM contains the PC BIOS, selftest program, and the CMOS
setup.
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