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EPC-7 Hardware Reference
ECL Trigger / Misc Reg ES1 ES0 ED1 ED0 VXR SBER 1
BSAM
815B
This read/write register contains the following bits:
ES Read-only bits that show the state of the ECL trigger lines on the backplane
(1 meaning asserted).
ED A 1 asserts the corresponding ECL trigger.
VXR VXI reset. This bit is cleared by an assertion of the VXI SYSRESET signal,
by setting the RSTP bit in the status/control register, or by other hardware
reset conditions (reset pushbutton, watchdog timer reset). It is a sticky bit
that remains clear until set by software. This bit drives the bit of the same
name in the event state register, one purpose of which is to give software the
opportunity to handle reset as an interrupt. When this bit is cleared, it affects
several other bits and registers. Please refer to the section
Reset Behavior in
Chapter 5 for more information.
SBER "Sticky BERR." This bit is cleared whenever a VXI data-transfer bus access
by the EPC-7 is terminated by a BERR. By initially setting the bit and then
performing a series of data transfers, software can determine if a bus error
occurred. (Alternatively, software could examine the BERR bit in the event
state register after each access, or enable the BERR event to generate an
interrupt.)
7 7
BSAM This bit is 0 if a pipelined write is active from the EPC-7 onto the VXI data-
transfer bus. It allows software to wait for the completion of a write (e.g., to
determine when SBER can safely be examined after a series of writes).
Unique Logical Addr Reg 815C
This register contains the EPC-7's ULA. Until a value is stored in this register, the
EPC-7's register base in the A16 space is FFC0, and it responds only when its
MODID is asserted. The ULA is changed by writing into this register or into the ID
register).
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