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EPC-7 Hardware Reference
Whenever the EPC-7 is held in the reset state, EVME is masked off (but
the register bit is not changed).
Bit 0 Set to 0.
7 7
Memory Mode Register
MDFF MDCF
RAM MEMS RAM RAM 8104
This register controls certain DRAM operational parameters.
MDFF When set (1), the 00FFxxxx region of memory is treated as normal DRAM.
When 0, reads to this region are mapped into the ROM area of the address
space.
MDCF This bit controls accesses to the 000Cxxxx and 000Fxxxx regions of the
address space. The former is where a video BIOS and SCSI BIOS typically
reside and the latter is where the ROM BIOS resides. When set (1), writes
to these regions are mapped to the EXMbus and reads come from DRAM.
When 0, writes are mapped to DRAM and reads from 000Cxxxx are mapped
to the EXMbus and reads from 000Fxxxx are mapped to DRAM. This bit is
used by the BIOS to copy itself and video and SCSI BIOS's into DRAM.
MEMS These bits control the address decoding (i.e., which addresses map to
DRAM versus the EXMbus). They are set by the BIOS with the following
encoding:
000 invalid (DRAM disabled)
001 invalid (DRAM disabled)
010 2 MB
011 4 MB
100 8 MB
101 16 MB
110 32 MB
111 64 MB
ID Register, lower 1 1 1 0 1 1 0 0 8140
ID Register, upper 1 0 0 A32 1 1 1 1 8141
This read-only register defines the EPC-7 as a message-based device with the
manufacturer being RadiSys Corporation (manufacturer code 4076).
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