1269 User Manual
Using The Enhanced Monitoring System 4-13
Table 4-6, VXI Condition and Event Register Bit Assignments
Bit
Set When
0
VXI Bus Error (BERR*) Count exceeds limit
1
VXI SYSFAIL* is asserted
2
VXI ACFAIL* is asserted
3
VXI IACK1 Count exceeds limit
4
VXI IACK2 Count exceeds limit
5
VXI IACK3 Count exceeds limit
6
VXI IACK4 Count exceeds limit
7
VXI IACK5 Count exceeds limit
8
VXI IACK6 Count exceeds limit
9
VXI IACK7 Count exceeds limit
The “Event Register” holds the latched status of each of the
individual items monitored. Each “Event Register” has the
same bit assignment as the corresponding “Condition
Register”. Thus, the “Voltage Event Register” has the same bit
assignment as that shown in
Figure 4-1.
The difference between the “Condition Register” and the “Event
Register” is that the “Event Register” holds
latched
status
information, while the “Condition Register” holds the
present
status information. For example, if the -12V power supply
voltage goes out of tolerance and then returns in tolerance, bit
6 of the “Voltage Condition Register” will be 0 while bit 6 of the
“Voltage Event Register” will be 1.
The following queries may be used to read the various
attributes’ Event Registers:
STAT:QUES:VOLT:EVENT?
-- Voltage Event Register
STAT:QUES:TEMP:EVENT?
-- Temperature Event Reg.
STAT:QUES:FREQ:EVENT?
-- Fan Speed Event Reg.
STAT:QUES:TIME:EVENT?
-- Elapsed Time Event Reg.
STAT:QUES:VXI:EVENT?
-- VXI Event Register
Each time the “Event Register” is read, the bits of the “Event
Register” are cleared. The bits of the “Event Register” are only
set on a transition from an in-tolerance state to out-of-tolerance
state. This corresponds to a 0-to-1 transition of the “Condition
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