LTE Standard Module Series
EC25 Hardware Design
EC25_Hardware_Design 61 / 130
3.14.1. WLAN Interface
EC25 provides a low-power SDIO 3.0 interface and control interface for WLAN design.
SDIO interface supports SDR mode (up to 50MHz).
As SDIO signals are very high-speed, in order to ensure the SDIO interface design corresponds with the
SDIO 3.0 specification, please comply with the following principles:
It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal
trace is 50
Ω
±10%.
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DCDC signals, etc.
It is recommended to keep matching length between CLK and DATA/CMD less than 1mm and total
routing length less than 50mm.
Keep termination resistors within 15
Ω
~24
Ω
on clock lines near the module and keep the route
distance from the module clock pins to termination resistors less than 5mm.
Make sure the adjacent trace spacing is 2 times of the trace width and bus capacitance is less than
15pF.
3.14.2. BT Interface*
EC25 supports a dedicated UART interface and a PCM interface for BT application.
Further information about BT interface will be added in future version of this document.
“*” means under development.
3.15. ADC
Interfaces
The module provides two analog-to-digital converter (ADC) interfaces.
AT+QADC=0
command can be
used to read the voltage value on ADC0 pin.
AT+QADC=1
command can be used to read the voltage
value on ADC1 pin. For more details about these AT commands, please refer to
document [2]
.
In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.
NOTE
