QDI Brilliant IV, Руководство пользователя

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Chapter 7
37
1
not affected by this bit.
Without additional wait state.
•
EDO RASx# Wait
State
2
1
One additional wait state is inserted before
RASx# is asserted for row misses. This
provides one clock of additional MAX[13:0]
setup time to RASx# assertion. This bit does
not affect page misses since the MAX[13:0]
lines are setup several clocks in advance of
RASx# assertion for page misses.
Without additional wait state.
•
SDRAM CAS Latency
Time
2
3
Defines the CLT timing parameter of SDRAM
expressed in the bus speed (eg. 100 MHz
clocks). Latency Time=2 clocks
Latency Time=3 clocks
•
DRAM Data Integrity
Mode
ECC Provides ECC (Error Checking and Correction)
function.
Non-ECC Disables ECC function.
•
System BIOS
Cacheable
Enabled Beside conventional memory, the system BIOS
area is also cacheable.
Disabled The system BIOS area is not cacheable.
•
Video RAM
Cacheable
Enabled Beside conventional memory, video BIOS area
is also cacheable.
Disabled Video BIOS area is not cacheable.
•
8 Bit I/ O Recovery
Time
1
∼
8 Defines the ISA Bus 8 bit I/O operating
recovery time.
NA 8 bit I/O recovery time does not exist.
•
16 Bit I / O
Recovery Time
1
∼
4 Defines the ISA Bus 16 bit I/O operating
recovery time.
NA 16 bit I/O recovery time does not exist.
•
AGP Aperture Size
(MB)
4
∼
256 Sets the effective size of the Graphics Aperture
to be used in the particular PAC
Configuration.
•
Auto Detect
DIMM/PCI Clk
Enabled
Disabled
Enables Auto Detect DIMM/PCI Clk, it is
helpful in reducing EMI.
Disables this function.