Chapter 5
17
Clear CMOS
¸
Power down the AC
supply then close once
Normal
JP3
Clear CMOS
JP3
Warning : You must shut down the
power supply first when
you want to clear the CMOS.
Memory Configuration
The P6I440BX/DP Brilliant IV main board supports up to four 168PIN 3.3V
un-buffered 100MHz/66MHz DIMM, provides a flexible size from 8MB up to
512MB SDRAM memory or 8MB up to 1GB Registered SDRAM memory.
The following set of rules enables optimum configurations.
Rules for populating a 440BX memory array:
,
DIMM sockets can be populated in any order.
,
Using the serial presence detect (SPD) data structure, programmed into
an E
2
PROM on the DIMM, the BIOS can determine the SDRAM’S size
and speed.
,
The DRAM Timing register, which provides the DRAM speed grade
control for the entire memory array, must be programmed to use the
timings of the slowest DRAMs installed.
,
Pentium® II processors with 100MHz bus speed should be paired only
with 100MHz SDRAM.
,
Possible SDRAM memory size is 8MB, 16MB, 32MB, 64MB, 128MB
in each DIMM socket.
Содержание Brilliant IV
Страница 1: ...PENTIUM IIP6I440BX D P Brilliant IV...
Страница 12: ...Introduction 6 This page is intentionally left blank...
Страница 14: ...Power Supply Requirements 8 This page is intentionally left blank...
Страница 19: ...Chapter 4 13 Note Please refer to chapter 5 for details on jumper setting...
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Страница 22: ......
Страница 28: ...System Setting by Jumper 20 This page is intentionally left blank...
Страница 63: ...Appendix 55 4 Insert Pentium II Processor in Slot1 Big HSSBASE...