Protac PRoX-2622, Руководство пользователя

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Chapter 5 Award BIOS Setup
Page: 5-14
Prox-2622 USER
′
S MANUAL
EDO DRAM SPEED SELECTION:
The DRAM timing is controlled by the DRAM Timing Registers. The
timings programmed into this register are dependent on the system design.
Slower rates may be required in certain system designs to support loose
layouts or slower memory. The available choices are 50ns and 60ns.
EDO CASx# MA WAIT STATE:
You can select the timing control type of EDO DRAM CAS MA. (memory
address bus) The choices are 1 and 2.
EDO RASx# WAIT STATE:
You can select the timing control type of EDO DRAM RAS MA (memory
address bus). The choices are 1 and 2.
SDRAM RAS-to-CAS DELAY:
You can select RAS to CAS Delay time in HCLKs of 2/2 or 3/3. The system
board designer should set the values in this field, depending on the DRAM
installed. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU.
The choices are 2 and 3.
SDRAM RAS PRECHARGE TIME:
Defines the length of time for Row Address Strobe is allowed to precharge.
SDRAM CAS LATENCY TIME:
You can select CAS latency time in HCLKs of 2/2 or 3/3. The system board
designer should set the values in this field, depending on the DRAM
installed. Do not change the values in this filed unless you change
specifications of the installed DRAM or the installed CPU.
DRAM DATA INTEGRITY MODE:
Select parity or ECC (error-correcting code), according to the type of
installed DRAM.
SYSTEM BIOS CACHEABLE :
Select Enabled allows caching of the system BIOS ROM at F000h-FFFFFh,
resulting in better system performance. However, if any program writes to
this memory area, a system error may result.