32
PG-200 Operation Manual
Version 2.D
boards do not have to be removed to change jumpers. Refer to Figure 1 (page 32) and
Figure 2 (page 36) for jumper field locations.
The jumper fields are as follows.
INT TRIG OUT
– Located on the Front Panel Board. Normally configured for 5 V
negative logic output but can be reconfigured for 5 V positive logic, 15 V positive or
negative logic. The JUMPERS program must be run for proper calibration following a
jumper change.
Delayed Trigger Out Jumper Field
Inhibit Gate Total Jumper Field
Internal Trigger Out Jumper Field
DELAY OUT
– Located on the Front Panel Board. Normally configured for 5 V
negative logic output but can be re-configured for 5 V positive logic, 15 V positive or
negative logic. The JUMPERS program must be run for proper calibration following a
jumper change.
DELX
– Located on the Processor Board. Normally configured for 5 V negative logic
output but can be reconfigured for 5 V positive logic.
INH GATE TOT
– Located on the Front Panel Board. When this jumper is inserted,
high voltage gate pulses will be immediately disabled upon receipt of an inhibit pulse.
Normally this jumper is removed and when an inhibit signal is received during a high
voltage gate pulse, the gate pulse is not truncated.
Figure 5.
PG-200 Front
Panel Board.
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