PRA-BD11
10
1
2
3
4
1
2
3
4
C
D
F
A
B
E
3. BLOCK DIAGRAM AND SCHEMATIC DIAGRAM
3.1 BLOCK DIAGRAM
Main Device
• SDI section
• AES/EBU section
• Common section
∗
1
Note ;
∗
1 : 27MHz clock from PRV-LX1
∗
2 : 27MHz clock to PRV-LX1
∗
2
IC
Name
Function
IC8103 (GS9025A)
SDI Receiver
SDI Receiver receive a SDI signal, and extract the 270MHz clock and equalize the signal.
IC8108 (GS9020A)
SDI Decoder
SDI Decoder receive the output of SDI Receiver, and perform the serial/parallel conversion and
27MHz clock generation.
IC8106 (GS9023A)
Audio Processor
Audio Processor demultiplex the video/audio signal from the SDI parallel, and each output it.
IC
Name
Function
IC8301 (CS8414-CS)
AES/EBU
Receiver
AES/EBU Receiver receive an AES/EBU signal, and judge a format.
Then generate audio data and output it.
IC
Name
Function
IC8201
(XC2S50-5PQ208C)
FPGA
FPGA convert a format of the video signal and the audio signal which extracted from SDI and
AES/EBU signals.
Switching control of 27MHz main clock of PRV-LX1, and the control of each IC.
CN8101
BNC
Connector
CN8203
FFC (30P)
IC8103
GS9025A
SDI Receiver
• SDO
• SDO#
• SCO
• SCO#
• 20 DOUT [0:9]
• PCLKOUT
• AOUTA
• AOUTB
• WCOUT
• 23 DOUT [0:9]
Digital Video Data
MAIN Clock
Select
• PCLKOUT (27MHz)
SDI IN
IC8108
GS9020A
SDI Decoder
IC8205
PE9016A
PROM
X8301
27MHz OSC
IC8106
GS9023A
Audio Processor
IC8306
5V
→
3.3V
Regulator
IC8203
27MHz
Clock Select
IC8201
XC2S50-5PQ208C
FPGA
CN8301
BNC
Connector
IC8301
CS8414-CS
AES/EBU Receiver
• 14 SDATA
• 14 FSYNC
• 14 SCK
AES/EBU
IN
SDI Embedded Digital Audio Data
AES/EBU Digital Audio Data
+5V
+5V
+3.3V
IC8307
5V
→
2.5V
Regulator
+2.5V
GND
SDI Video
Format det.
Copy protect det.
SDI Audio
Format det.
AES/EBU
Format det.
Control
Device etc.
Control BUS
JTAG BUS
CN8202
FFC (26P)
CN8201
PH (4P)
From AVIB
From AVIB
From AVIB
PRA-BD11
Содержание PRA-BD11
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