PDP-507CMX
68
1
2
3
4
1
2
3
4
C
D
F
A
B
E
No signal
With signal
AC power ON
(Power coad
connected to the
wal outlet)
Basic operation(Numerical unit:Vdc; except for case whwn units are individually indicated)
Power
management
Standby
Name
Pin No.
Pin name
FuNon-connection termialtion
Signal direction
(DR : Data Relay)
MAIN POWER "ON"
Main power
OFF
AC Power OFF
(Power cord
pulled out of the
wall outlet
e
d
o
m
o
e
d
i
V
0
S
D
V
L
-
E
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
-
E
R
7
1
LVDS serial
differential E-
output 0Vac; Bias
1.4Vdc
Video mode
LVDS serial
differential E-
output 0.3Vac;
Bias 1.25Vdc
0
0
0
-
MAIN LVDS
e
d
o
m
o
e
d
i
V
0
S
D
V
L
+
D
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
+
D
R
8
1
LVDS serial
differential D+
output 0Vac; Bias
1.1Vdc
Video mode
LVDS serial
differential D+
output 0.3Vac;
Bias 1.25Vdc
0
0
0
-
MAIN LVDS
e
d
o
m
o
e
d
i
V
0
S
D
V
L
-
D
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
-
D
R
9
1
LVDS serial
differential D-
output 0Vac; Bias
1.4Vdc
Video mode
LVDS serial
differential D-
output 0.3Vac;
Bias 1.25Vdc
0
0
0
-
MAIN LVDS
k
c
o
l
c
a
t
a
d
o
e
d
i
V
0
S
D
V
L
+
k
c
o
l
c
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
+
K
L
C
R
0
2
LVDS serial
differential
clock+output
0.3Vac; Bias
1.25Vdc
Video data clock
LVDS serial
differential
clock+output
0.3Vac; Bias
1.25Vdc
0
0
0
-
MAIN LVDS
k
c
o
l
c
a
t
a
d
o
e
d
i
V
0
S
D
V
L
-
k
c
o
l
c
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
-
K
L
C
R
1
2
LVDS serial
differential clock-
output 0.3Vac;
Bias 1.25Vdc
Video data clock
LVDS serial
differential clock-
output 0.3Vac;
Bias 1.25Vdc
0
0
0
-
MAIN LVDS
22
GND
GND
LVD S
0
0
0
0
0
0
0
-
S
D
V
L
a
t
a
d
o
e
d
i
V
0
S
D
V
L
+
C
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
+
C
R
3
2
serial differential
C+ output
0.3Vac: Bias
1.25Vdc
Video data LVDS
serial differential
C+ output
0.3Vac: Bias
1.25Vdc
0
0
0
-
MAIN LVDS
S
D
V
L
a
t
a
d
o
e
d
i
V
0
S
D
V
L
-
C
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
-
C
R
4
2
serial differential
C- output 0.3Vac:
Bias 1.25Vdc
Video data LVDS
serial differential
C- output 0.3Vac:
Bias 1.25Vdc
0
0
0
-
MAIN LVDS
S
D
V
L
a
t
a
d
o
e
d
i
V
0
S
D
V
L
+
B
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
+
B
R
5
2
serial differential
B+ output 0Vac:
Bias 1.1Vdc
Video data LVDS
serial differential
B+ output
0.3Vac: Bias
1.25Vdc
0
0
0
-
MAIN LVDS
S
D
V
L
a
t
a
d
o
e
d
i
V
0
S
D
V
L
-
B
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
-
B
R
6
2
serial differential
B- output 0Vac:
Bias 1.4Vdc
Video data LVDS
serial differential
B- output 0.3Vac:
Bias 1.25Vdc
0
0
0
-
MAIN LVDS
S
D
V
L
a
t
a
d
o
e
d
i
V
0
S
D
V
L
+
A
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
+
A
R
7
2
serial differential
A+ output 0Vac:
Bias 1.1Vdc
Video data LVDS
serial differential
A+ output
0.3Vac: Bias
1.25Vdc
0
0
0
-
MAIN LVDS
S
D
V
L
a
t
a
d
o
e
d
i
V
0
S
D
V
L
-
A
t
u
p
t
u
o
m
e
t
s
y
s
o
e
d
i
V
-
A
R
8
2
serial differential
A- output 0Vac:
Bias 1.4Vdc
Video data LVDS
serial differential
A- output 0.3Vac:
Bias 1.25Vdc
0
0
0
-
MAIN LVDS
29
GND
GND
LVD S
0
0
0
0
0
0
-
30
GND
GND
LVD S
0
0
0
0
0
0
-
31
GND
GND
LVD S
0
0
0
0
0
0
-
AD
1
GND
GN
M
D
AIN
0
0
0
0
0
0
-
N
I
A
M
D
N
G
D
N
G
2
2
0
5
8
N
C
0
0
0
0
0
0
-
3
P_ST_B
Connecting detection
PDP
MAIN
MAIN
0
0
0
0
0
0
LVD S
MAIN
4
MR_ST_B
Connecting detection
MAIN PDP
MAIN
0
0
0
0
0
0
0
0
0
0
0
0
0
MAIN LVDS
5
NC
Non-connection termial
MAIN
-
-
-
-
-
-
-
-
6
MR_RXD
UART data
PDP
MAIN
l
a
n
g
i
s
k
c
o
l
C
0
N
I
A
M
(3.3Vac) when
data are
received; 3.3Vdc
when no data are
received.
Clock signal
(3.3Vac) when
data are
received; 3.3Vdc
when no data are
received.
3.3
3.3
3.3
-
LVD S
MAIN
7
V+3V_D
3.3V power supply for the
test jig
0
0
0
3
.
3
3
.
3
3
.
3
3
.
3
3
.
3
3
.
3
3
.
3
3
.
3
3
.
3
3
.
3
0
N
I
A
M
-
-
8
AC_DET_B
AC power detection from
power supply
MAIN
0
-
LVD S
MAIN
9
NC
Non-connection termial
MAIN
-
-
-
-
-
-
-
-
10
REQ
UART send request from
PDP module
n
e
h
w
c
d
V
3
.
3
0
N
I
A
M
riquest signal is
received; 0Vdc
when no riquest
signal is
received.
3.3Vdc when
riquest signal is
received; 0Vdc
when no riquest
signal is
received.
0
0
0
-
LVD S
MAIN
11
NC
Non-connection termial
MAIN
-
-
-
-
-
-
-
-
12
MR_TXD
UART data
MAIN PDP
l
a
n
g
i
s
k
c
o
l
C
0
N
I
A
M
(3.3Vac) when
data are
received; 3.3Vdc
when no data are
received.
Clock signal
(3.3Vac) when
data are
received; 3.3Vdc
when no data are
received.
-
MAIN LVDS
13
NC
Non-connection termial
MAIN
-
-
-
-
-
-
-
-
14
STB_MUTE
Stand by power control
signal
-
0
7
.
4
7
.
4
0
0
0
N
I
A
M
MAIN LVDS
15
NC
Non-connection termial
MAIN
-
-
-
-
-
-
-
-
16
VIS
reserve
MAIN
0
0
0
0
0
0
MAIN LVDS
17
NC
Non-connection termial
MAIN
-
-
-
-
-
-
-
-
18
FIELD
Advanced cinema control
signal
MAIN
0
0
0
0
0
0
MAIN LVDS
19
GND
GN
M
D
AIN
0
0
0
0
0
0
-
20
GND
GN
M
D
AIN
0
0
0
0
0
0
-
AD
1
GND
GND
LVD S
0
0
0
0
0
0
-
CN102
2
P ST B
No use
LVD S
0
0
0
0
0
0
0
0
0
0
0
0
-
3
NC
Non-connection termial
LVDS
-
-
-
-
-
-
-
-
4
V+3V_D
3.3V power supply for the
test jig
0
0
0
3
.
3
3
.
3
0
S
D
V
L
-
-
5
NC
Non-connection termial
LVDS
-
-
-
-
-
-
-
-
6
NC
Non-connection termial
LVDS
-
-
-
-
-
-
-
-
7
NC
Non-connection termial
LVDS
-
-
-
-
-
-
-
-
Содержание PDP 507CMX
Страница 18: ...PDP 507CMX 18 1 2 3 4 1 2 3 4 C D F A B E 2 6 PANEL CHASSIS SECTION 1 9 2 11 4 7 7 7 7 7 3 7 10 8 7 10 7 6 5 ...
Страница 44: ...PDP 507CMX 44 1 2 3 4 1 2 3 4 C D F A B E 4 2 OVERALL CONNECTION DIAGRAM 2 2 ...
Страница 45: ...PDP 507CMX 45 5 6 7 8 5 6 7 8 C D F A B E ...
Страница 84: ...PDP 507CMX 84 1 2 3 4 1 2 3 4 C D F A B E 500ns div 500ns div 200ns div ...
Страница 104: ...PDP 507CMX 104 1 2 3 4 1 2 3 4 C D F A B E ...
Страница 108: ...PDP 507CMX 108 1 2 3 4 1 2 3 4 C D F A B E ...
Страница 208: ...PDP 507CMX 208 1 2 3 4 1 2 3 4 C D F A B E THC63LVD104AF K IC101 LVDS ASSY LVDS Receiver Block Diagram Pin Function ...
Страница 209: ...PDP 507CMX 209 5 6 7 8 5 6 7 8 C D F A B E MP2367DN LF IC302 DD ASSY Converter IC Block Diagram Pin Function ...
Страница 210: ...PDP 507CMX 210 1 2 3 4 1 2 3 4 C D F A B E NCP5211BDG IC303 DD ASSY Regulator IC Block Diagram Pin Function ...