PDP-507CMX
204
1
2
3
4
1
2
3
4
C
D
F
A
B
E
OC1
OC2
OUT
L
L
ALL Hi-Z
L
H
DATA
H
L
ALL L
H
H
ALL H
No.
Pin Name
Pin Function
I/O
1 - 30
OUT3 - OUT32
O
High-voltage push-pull output
31
N.C.
−
Not used
32 - 33
V
DDH
−
Power for High-voltage circuit
34
N.C.
−
Not used
35 - 37
GND1
−
GND
38
N.C.
−
Not used
39
GND2
−
GND
40 - 41
GND1
−
GND
42
N.C.
−
Not used
43 - 44
V
DDH
−
Power for High-voltage circuit
45
N.C.
−
Not used
46 - 77
OUT33 - OUT64
O
High-voltage push-pull output
78
N.C.
−
Not used
79 - 80
V
DDH
−
Power for High-voltage circuit
81
N.C.
−
Not used
82 - 83
GND1
−
GND
84
DIR
I
85
SO
I/O
Serial data In/Out
86
CLK
I
87
LAT
I
88
V
DD
−
Power for Logic circuit
89
OC1
I
Output control
Output is controlled by truth table right side.
Setting the shift direction of shift-register
L : reverse side shift (SO
→
SI), H : forward side shift (SI
→
SO)
LAT data Input
L : The data of shiftregister is transferred to ouput latch.
H : The ouput data of latch is holded.
Serial clock Input Down-side edge trigger
90
OC2
I
91
SI
I/O
Serial data In/Out
92
CLR
I
All output reset CLR terminal : L
→
normal operation, CLR terminal : H
→
All output "H"
93 - 94
GND1
−
GND
95
N.C.
−
Not used
96 - 97
V
DDH
−
Power for High-voltage circuit
98
N.C.
−
Not used
99 - 100
OUT1 - OUT2
O
High-voltage push-pull output
PIN FUNNCTION
Содержание PDP 507CMX
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Страница 44: ...PDP 507CMX 44 1 2 3 4 1 2 3 4 C D F A B E 4 2 OVERALL CONNECTION DIAGRAM 2 2 ...
Страница 45: ...PDP 507CMX 45 5 6 7 8 5 6 7 8 C D F A B E ...
Страница 84: ...PDP 507CMX 84 1 2 3 4 1 2 3 4 C D F A B E 500ns div 500ns div 200ns div ...
Страница 104: ...PDP 507CMX 104 1 2 3 4 1 2 3 4 C D F A B E ...
Страница 108: ...PDP 507CMX 108 1 2 3 4 1 2 3 4 C D F A B E ...
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