Pioneer PDP-504CMX, Руководство по обслуживанию

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PDP-504CMX/1
183
5 6 7 8
5 6
7
8
C
D
F
A
B
E
Output Pins
Differential Signal Data Pins
Pin Name No. Type Function
QE23 - QE0
37-30,
27-20,
17-10
Out
Output Even Data[23:0] corresponds to 24-bit pixel data for one pixel per clock input mode and to
the first 24-bit pixel data for two pixels per clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the input
data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
QO23 - QO0
77,
75-69,
66-59,
56-49
Out
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for two pixels per clock mode.
During one pixel per clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
ODCK 44 Out
Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on PD# or
PDO# will put the output driver into a high impedance (tri-state) mode. A weak internal pulldown
device brings the output to ground.
DE 46 Out
Output Data Enable. This signal qualifies the active data area. A HIGH level signifies active
display time and a LOW level signifies blanking time. This output signal is synchronized with
the output data. A low level on PD# or PDO# will put the output driver into a high impedance
(tri-state) mode. A weak internal pull-down device brings the output to ground.
HSYNC
VSYNC
CTL1
CTL2
CTL3 48
47
40
41
42
Out
Horizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This output is not powered down by PDO#.
General output control signal 2.
General output control signal 3.
A low level on PD# or PDO# will put the output drivers (except CTL1 by PDO#) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
Pin Name No. Type Function
RX0+
RX0-
RX1+
RX1-
RX2+
RX2- 90
91
85
86
80
81
Analog Receiver Differential Data Pins. TMDS Low Voltage Differential Signal input data pairs.
RXC+
RXC- 93
94
Analog Receiver Differential Clock Pins. TMDS Low Voltage Differential Signal input clock pair.
EXT_RES 96 Analog
Impedance Matching Control. An external 390
Ω
resistor must be connected between AVCC
and this pin.
Pin Function