PDP-504CMX/1
179
5
6
7
8
5
6
7
8
C
D
F
A
B
E
SYNCSEP
SYNCTIP
CLP
SW
SOGT
SOGIN2
SOGOUT
ADDRESS
SDA
SCL
XSENABLE
SEROUT
UNLOCK
HOLD
XTLOAD
RC1
EVEN/ODD
DATA MODE
DSYNC/DIV
OUT
3WIRE/I
2
C
XPOWER SAVE
SYNCSEP
SYNCSEP
AMP B
REGISTER
PD
FINE
DELA
Y
(6)
SOGIN1
SOGIN2
SOGIN1
B/CbIN2
B/CbCLP
B/CbIN1
SW
SOGP
SW
PLL
V
TH
(4)
V
HYS
(2)
Main Contr
ast (8)
Cb Offset (6)
Sub Br
ightness (8)
Sub Contr
ast (8)
SW
B
SW
CP (3)
VCO
1/2DIV
ADC B
ADC G
ADC R
PLL
Width
(2)
CO
ARSE
DELA
Y (2)
COUNTER (12)
DIV
1, 2, 4, 8
SW
SYNCIN
SW
SOGO
RC2
1/2XCLK
1/2CLK
CLK
BA7 - BA0
BB7 - BB0
GA7 - GA0
GB7 - GB0
RA7 - RA0
RB7 - RB0
VRB
XCLK
VRB
VRT
R/CrOUT
SW
G/YOUT
SW
B/CbOUT
CLPIN
VR
T
AMP G
G/YIN2
G/YIN1
Sub Br
ightness (8)
Sub Contr
ast (8)
SW
G
AMP R
R/CrIN2
R/CrIN1
Cr Offset (6)
Sub Br
ightness (8)
Sub Contr
ast (8)
SW
R
G/YCLP
R/CrCLP
Block Diagram
Содержание PDP-504CMX
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