PDP-501MX, PDP-V501X
48
1
2
3
4
5
6
7
8
9
10 11 12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
IOGND
CXA3106Q
IOVcc
PLLVcc
PLLGND
VCOVcc
VCOGND
VCOHGND
IREF
RC2
IRGND
RC1
IRVcc
DSYNC
CLK
CLKN
CLK/2
CLK/2N
DGND
DVcc
UNLOCK
DIVOUT
SEROUT
CS
TLOAD
PECL
V
CC
VBB
DSYNCH
DSYNCL
CLKH
CLKL
CLK/2H
CLK/2L
PECL
V
CC
IOGND
TTL
V
CC
TTLGND
IO
Vcc
IOGND
VCOH
VCOL
VCO
HOLD
SYNCH
SYNCL
SYNC
SENABLE
SCLK
S
D
ATA
VCO
(TTL)
VCO
(PECL)
SYNC
(TTL)
SYNC
(PECL)
HOLD
(TTL)
IRFF
SENABLE
SCLK
SDATA
read out
TTL OUT
SER OUT
on/off 1bit
TTL OUT
DIV OUT
TTL IN
TLOAD
1bit
CS
VBB
UNLOCK
CLK/2
(PECL)
NCLK/2
(TTL)
CLK/2
(TTL)
CLK
(PECL)
NCLK
(TTL)
CLK
(TTL)
DSYNC
(TTL)
DSYNC
(PECL)
RC1
RC2
1/256~1/4096 CLK
1/16~20/16 CLK
12bit
1bit
2bit
5bit
RSET
TTL OUT
1bit
on/off 1bit
PECL OUT
Polarity
1~4 CLK
2bit
1bit
2bit
TTL OUT
on/off 1bit
1bit
Coarse
Delay
Latch
Logic
TTL OUT
on/off 1bit
PECL OUT
TTL OUT
on/off 1bit
on/off 1bit
TTL OUT
on/off 1bit
PECL OUT
on/off 1bit
PECL
unlock
detect
1/2
whole chlp
power save
synthesizer
power save
DIV
MUX
VCO
Fine
Delay
Charge
Pump
Phase
Detector
Polarity
TTL IN
TTL IN
PECL IN
TTL IN
PECL IN
Programmable
Counter
DAC
CONTROL REGISTER
¶
Pin Assignment
7
CXA3106Q
(DIGITAL VIDEO ASSY: IC1242)
PLL IC
¶
Block Diagram
Содержание PDP-501MX
Страница 16: ...PDP 501MX PDP V501X 16 A B C D 1 2 3 4 1 2 3 4 3 3 POWER SUPPLY MODULE 1 2 J 1 2 ...
Страница 17: ...PDP 501MX PDP V501X 17 A B C D 5 6 7 8 5 6 7 8 J 1 2 ...
Страница 18: ...PDP 501MX PDP V501X 18 A B C D 1 2 3 4 1 2 3 4 3 4 POWER SUPPLY MODULE 2 2 J 2 2 ...
Страница 19: ...PDP 501MX PDP V501X 19 A B C D 5 6 7 8 5 6 7 8 J 2 2 ...