CDJ-1000MK2
82
1
2
3
4
1
2
3
4
C
D
F
A
B
E
2
3
1
t1
t2
t3
t4
t5
t6
t7
t8
t8
XRST (Hardware reset)
PRGM (/PROGRAM)
XINT (FPGA I/O)
S2CK53 (S2CK)
(FPGA input)
DSP serial common use
FPGA Prog
download
(CLK2.5MHz)
S2DO3N (S2DO)
(FPGA input)
DSP serial common use
DONE
Flag indicating
completion of downloading
of the FPGA Prog
HACK
DSP2 download
OK flag
SD04_1
DSP2 download
OK flag
DGP2
DSP download
OK flag
XFRST
(FPGA register clear)
XSRST
(DSP reset)
S2CK3 (S2CK)
(DSP input)
Reversed signal of the
FPGA input
XSS23 (XSS2)
(DSP2 CS)
XSS13 (XSS1)
(DSP1 CS)
A
The dotted line shows a case
when downloading fails.
Reloading of the FPGA Prog
Approx. 600 ms
Measurement 1
µ
s, spec 300 ns (min)
DSP2 initial
download
DSP2 main Prog
download
DSP1 main Prog
download
DSP1 initial
download
If /INT becomes L (CRC NG) at
A
, it is judged that
downloading of the FPGA Prog failed, and the sequence is
restarted from
1
. Max. retries: 5
If DGP2 does not become L within 6 ms after XSS1 is set to H, it is judged that the
initial downloading of the DSP failed, and the sequence is restarted from FPGA
downloading. If DSP2 fails, HACK does not become L. Max retries: 2