Debugging
© PHYTEC Meßtechnik GmbH 2002 L-586e_2
53
The following figure (see Figure 4) depicts the memory layout that is
configured by the Raisonance monitor for 64 kByte RAM.
Figure 4:
Memory Model for Use with the Raisonance Monitor
(64 kByte RAM)
Note:
When using the von Neumann memory architecture, ensure that the
CODE and XDATA areas within the application program do not
overlap. This is important because otherwise portions of the program
(CODE) will be overwritten by e.g. variables (XDATA), resulting in
an error when executing user code.
I/O Area (for details see Hardware Manual)
RAM for :
-------------
application CODE and XDATA
(monitor* CODE and XDATA)
(*included in application)
von Neumann XDATA portion of target
Monitor firmware (loader51.hex)
XDATA access
F000H
0000H
FFFFH
FBFFH
IO-AREA (PLD & /CS1..CS3
Read-Write (RAM)
EFFFH
FC00H
von Neumann
Содержание phyCORE-P87C591
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