Camera Serial Commands | NOCTURN XL Camera | 25
Name
Address Size
Description
12
DPLL_LOCKED
13
DPLL_UNDERFLOW
14
DPLL_OVERFLOW
15
VRAMP
CLKMATCH
34
8
Set compensation for channel-to-channel skew:
0
no compensation
254
maximum compensation
Note: ‘255’ is an invalid setting
PGA_GAIN
35
3
Set the analog gain in the column amplifier:
0
0.8
1
1.2
2
1.6
3
2.0
4
2.4
5
3.6
6
4.8
7
6.0
ADC_GAIN
36
6
Set the gain in the ADC
CHANNEL_EN
37
7
Disable/Enable output, clock and control channels:
Bit[0]-Bit[3]= Data channels
Bit[4]= Clock channel
Bit[5]= Control channel
Bit[6] = LVDS clock receiver
I_COLPC
38
4
Column load precharge current
I_COL
38
4
Column load current
I_COLAMP
39
4
Column amplifier current
I_ADC
39
4
ADC comparator current
I_COMPINV
40
4
ADC output invertor current limit
I_ADCPC
40
4
ADC precharge voltage buffer current
I_LVDS_REC
41
4
LVDS receiver current
I_LVDS_DRIV
41
4
LVDS driver current
V_ADCPC
42
7
ADC precharge voltage
V_ADCCLAMP
43
7
ADC clamp voltage
RST_LOW
44
7
Pixel reset low voltage
VTX_LOW0
45
7
Set the saturation/anti-blooming level for the
integration after slope 3.
VTX_LOW1
46
7
Set the reset level for the third slope. Change this
register to control the position of the knee point
between slope 2 and slope 3. Set the saturation/anti-
blooming level in case of dual slope operation.
VTX_LOW2
47
7
Set the reset level for the second slope. Change this
register to control the position of the knee point
between slope 1 and slope 2. Set the saturation/anti-
blooming level in case of single slope operation.
V_VRAMP2
48
7
Starting voltage of 2nd ramp in AD conversion
V_VRAMP1
49
7
Starting voltage of 1st ramp in AD conversion
V_VREF
50
7
Reference voltage for the column amplifier
V_TREF
51
7
Reference voltage for the reset conversion in
test_mode
V_TSIG
52
7
Reference voltage for the signal conversion in
test_mode
V_TEST_HIGH
53
6
Highest voltage adjustment of V_TREF and V_TSIG
PHOTONIS Digital Imaging LLC
NVT 200-LC-4019
6170 Research Road Suite 208
Revision: C.04
Frisco, TX USA 75033
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