66
TCM2.0E LA
7.
Circuit Diagrams and PWB Layouts
SSB v2: LVDS Receiver
GND
GND
VCC4
RXOUT21
RXOUT20
RXOUT19
GND5
RXOUT1
8
RXOUT17
RXOUT16
VCC
3
RXOUT15
RXOUT14
RXOUT1
3
GND4
RXOUT12
RXOUT11
RXOUT10
VCC2
RXOUT9
RXOUT
8
RXOUT7
GND
3
RXOUT6
RXOUT5
RXOUT4
RXOUT
3
VCC1
RXOUT2
RXOUT1
GND2
RXOUT0
RXCLKOUT
PWRDWN
PLLGND2
PLLVCC1
PLLGND1
LVD
S
GND
3
RXIN
3
+
RXIN
3
-
RXCLKIN-
RXIN2+
RXIN2-
LVD
S
GND2
LVD
S
VCC1
RXIN1+
RXIN1-
RXIN0+
RXIN0-
LVD
S
GND1
RXOUT27
RXOUT26
RXOUT25
GND1
RXOUT24
RXOUT2
3
RXOUT22
GND
GND
GND
GND
GND
A
1
2
3
4
5
6
7
8
F
E
D
C
B
A
8
7
6
5
4
3
2
1
F
E
D
C
B
1
2
3
4
5
6
7
8
R290
100R
1
2
3
4
5
6
7
8
R299
100R
1
2
3
4
5
6
7
8
R29
8
100R
1
2
3
4
5
6
7
8
R296
100R
1
2
3
4
5
6
7
8
R295
100R
1
2
3
4
5
6
7
8
R294
100R
1
2
3
4
5
6
7
8
R29
3
100R
C2015
0.01
0.1U
C2007
C2006
0.1U
C2004
0.1U
C2202
0.1U
C2001
L929
600R
C2010
0.1U
R291
10K
C2011
16P
R292
33
R
C0
3
0
10P
C029
10P
C0
3
2
10P
C027
10P
C026
10P
C015
10P
C021
10P
C0
3
1
10P
C02
8
10P
C025
10P
C024
10P
C4
10P
C02
3
10P
C022
10P
C020
10P
C019
10P
C01
8
10P
C017
10P
C014
10P
C01
3
10P
C012
10P
C011
10P
C016
10P
C010
10P
L2
3
9
120R
R24
100R
R2
3
100R
B
C
E
Q5
C14
3
ZT
PWRDN_EN
R2005
100R
R2004
100R
R200
3
100R
AP
33
AP
33
AN
33
AN
33
CLK11+
CLK11+
CLK11-
CLK11-
AN22
AP22
AN22
AN11
AP00
AP11
AP11
AN11
AP00
AN00
1
10
11
12
1
3
14
15
16
17
1
8
19
2
20
21
22
2
3
24
25
26
27
2
8
29
3
3
0
3
1
3
2
33
3
4
3
5
3
6
3
7
38
3
9
4
40
5
6
7
8
9
P205
56
55
54
5
3
52
51
50
49
4
8
47
46
45
44
4
3
42
41
40
3
9
38
3
7
3
6
3
5
3
4
33
3
2
3
1
3
0
29
2
8
27
26
25
24
2
3
22
21
20
19
1
8
17
16
15
14
1
3
12
11
10
9
8
7
6
5
4
3
2
1
U207
V
38
6
T_R1
T_R2
T_G0
T_R5
T_CLK
T_R0
T_H
S
YNC
T_B
3
T_B2
T_B1
T_B0
T_G7
T_G6
T_G5
T_G4
T_G
3
T_G2
T_R7
DV
33
A_LVD
S
_RECEIVER
DV
33
A
DV
33
A
DV
33
A
DV
33
A
T_B7
T_B6
T_B5
T_B4
T_G1
T_R6
T_R4
T_R
3
T_DE
T_V
S
YNC
AP22
AN00
PWRDN
DV
33
A_LVD
S
_RECEIVER
PWRDN
T_CLK
T_G6
R7
R6
R5
R4
R
3
R2
R1
G7
G6
G5
G0
B7
B6
B5
B4
B
3
DE
D_H
S
YNC
D_V
S
YNC
CLK
T_R7
T_R6
T_R5
T_R4
T_R
3
T_R2
T_R1
T_R0
T_G7
T_G5
T_G4
T_G
3
T_G2
T_G1
T_G0
T_B7
T_B6
T_B5
T_B4
T_B
3
T_B2
T_B1
T_B0
T_V
S
YNC
T_H
S
YNC
T_DE
R0
G4
G
3
G2
B2
B1
B0
G1
PANEL_CTL2
CLK
D_V
S
YNC
B6
B4
B2
B0
G6
G4
G2
R6
R4
DE
D_H
S
YNC
B7
B5
B
3
VDD_PANEL
G0
R2
R0
B1
G7
G5
G
3
G1
R7
R5
R
3
R1
1795
3
_5
3
9_090
33
0.ep
s
090
33
1
LVD
S
RECEIVER
B19
B19