Circuit Diagrams and PWB Layouts
33
TCM2.0E LA
7.
SSB v1: MT5335 Video Processor
T
T
T
T
A
1
2
3
4
5
6
7
8
F
E
D
C
B
A
8
7
6
5
4
3
2
1
F
E
D
C
B
T
S
DA
S
CL
WC
VCC
V
SS
E2/NC
E1/NC
E0/NC
GPIO_
3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_
8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_1
3
O
S
DA0
O
S
CL0
O
S
DA1
O
S
CL1
OPWM0
OPWM1
OPWM2
OPWR
S
B
OPCTRL0
OPCTRL1
OPCTRL2
OPCTRL
3
OPCTRL4
OPCTRL5
ORE
S
ET_
C_XREG
AVDD
33
_REG
ADIN0
ADIN1
ADIN2
ADIN
3
ADIN4
AVDD
33
_
S
RV
XTALI
XTALO
VCXO
AVDD
33
_XTAL
TXC
IIC ADDRE
SS
"A0"
Adj
us
t the power on timing
AVDD
33
_XTAL
R200 1
8
0K
POWER_ON
MT51
33
_RE
S
ET
CI_CLE
NC
R
3
7
CI_POWE#
207
20
8
209
59
60
210
211
212
214
215
216
204
205
6
3
62
191
202
20
3
72
92
91
76
75
90
8
9
71
8
7
88
14
8
149
150
151
152
147
144
14
3
146
145
U20
3
MT5
33
5PKU
EDID_PRT
EDID_PRT
CI_INT
LVD
S
VDD_EN
R
38
10K
R44
10K
R
3
6
10K
4K7
R
3
9
B
C
E
Q1
BT
3
904
R40
NC\0R
DV
33
DV
33
R201
4K7
B
C
E
Q200
BT
3
904
R20
3
10K
PANEL_
S
LT
ORE
S
ET#
C_XREG
PWRDET
O
S
DA0
O
S
CL0
O
S
DA0
O
S
CL0
O
S
DA1
O
S
CL1
BL_DIM
OPWM1
OXTALO
OXTALI
AVCC_
S
RV
KEY
S
CART_F
S
_IN
PWRDET
AVDD
33
_REG
C_XREG
ORE
S
ET#
S
W_UPDATE_CTL
HDMI_INT
CEC
BL_ON/OFF
AMP_MUTE
CI_ALE
CI_OEB
CI_PDD7
CI_PDD6
CI_PDD5
CI_PDD4
CI_PDD
3
X200
60M
C20
3
4U7
B
C
E
Q206
C124ET
DV
33
C221
10P
C222
10P
C22
3
1000P
L214
0.
8
2UH
C205
1U
C206
1U
5
6
7
8
4
3
2
1
U205
M24C16MN
R217
33
R
Z95
8
C201
220U
16V
L211
600R
L210
600R
L212
600R
C204
1U
D200
LL414
8
MTK_IC_RE
S
ET
OXTALI
DV
33
R209
1K
R20
8
220R
R210
47K
OXTALO
DV
33
C247
0.1U
R216
4K7
R215
4K7
R214
10K
DV
33
R204
10K
R205
10K
DV
33
DV
33
DV
33
DV
33
R211
NC
C226
0.1U
C224
0.1U
C225
0.1U
B
C
E
Q202
BT
3
904
R207
10R
R206
1K
B
C
E
Q201 BT
3
904
R202
10K
AVDD
33
_REG
AVCC_
S
RV
AVDD
33
_XTAL
Z956
Z957
Z960
Z959
OPWM2
KEY_5
33
5
MT5
33
5 VIDEO PROCE
SS
OR
B07
B07
I_17950_027.ep
s
07050
8