36
TCM2.0E LA
7.
Circuit Diagrams and PWB Layouts
SSB v1: Flash Memory
GND
GND
GND
POCE0_
POOE_
PDD0
PDD1
U0RX
U0TX
JTM
S
JTR
S
T_
JTCK
JTDO
JTDI
OIRI
PARB_
PDD2
VCCK
VCCK1
VCCK2
VCCK
3
VCCK4
VCCK5
VCCK6
VCCK7
VCC
3
IO_
3
VCC
3
IO_
3
_1
VCC
3
IO_
3
_2
DVDD10
DVDD10_1
E-PAD
VCC2IO
VCC2IO1
VCC2IO2
VCC2IO
3
VCC2IO4
VCC2IO5
VCC2IO6
VCC2IO7
VCC2IO
8
VCC2IO9
GND
GND
GND
GND
GND
GND
GND
GND
GND
PO2
VCC
NC
C
S
#
PO1
PO0
WP#/ACC
PO
3
GND
PO4
PO6
PO5
S
O
HOLD#
S
CLK
S
I
GND
0
0
A
B
C
D
5
4
3
2
1
D
C
B
A
1
2
3
4
5
Tr
a
p MODE
NORMAL MODE
ICE MODE
OPWM2
AOBLK
AOLRCK
0
0
0
1
0
TRAP MODE
CORE RE
S
ET 1 U
S
OPCTRL5
OPCTRL4
1
R
S
-2
3
2
C006
100U
6V
3
R90
10K
R2011
0R
R2012
0R
AV
33
R242
NC\4K7
+5V
OIRI_MT5
33
5
OIRI
4K7
R244
B
C
E
Q
3
BT
3
904
2
1
R
8
7
EZJZ1V270RA
1
2
3
4
P201
U0RX
R2
33
10K
4
2
3
7
5
6
9
11
10
12
14
1
3
8
1
16
15
U202
MX25L
3
205
1
2
3
45
6
7
8
R270
10K
1
2
4
6
8
12
14
16
1
8
20
10
3
5
7
9
11
1
3
15
17
19
P20
3
R2
3
5
1K
R2
3
9
33
R
10K
R2
38
R2
3
7
10K
10K
R2
3
6
C267
0.1U
AOLRCK
AOBCK
OPWM2
3
2
1
4
P200
PDD0
R245
0R
0.1U
C007
DV
33
CI_PDD2
CI_RB
C240
1U
1U
C2
3
5
L22
3
600R
R240
4K7
DDRV_IC
DDRV_IC
DV10
DV
33
DV
33
DV
33
DV10
DV
33
C264
0.1U
4K7
R241
JTR
S
T#
JTAG_DBGACK
JTAG_DBGRQ
TVTREF#1
JTDO
JTCK
JTM
S
JTDI
C265
0.1U
1U
C2
3
4
0.1U
C26
3
C262
0.1U
JTCK
JTM
S
JTR
S
T#
JTDI
U0RX
U0TX
POCE0#
OIRI_MT5
33
5
JTDO
POOE#
PDD0
PDD1
1U
C2
3
6
1U
C2
3
7
C270
0.1U
C269
0.1U
C26
8
0.1U
C272
0.1U
C271
0.1U
C279
0.1U
1U
C2
3
9
1U
C2
38
C27
8
0.1U
C277
0.1U
C275
0.1U
C274
0.1U
C27
3
0.1U
POOE#
PDD1
14
4
8
57
5
8
61
206
21
3
246
247
197
64
70
162
257
10
12
16
1
8
27
3
0
52
54
55
56
U20
3
MT5
33
5PKU
252
251
250
249
95
94
25
3
1
256
255
254
9
3
245
24
8
U20
3
MT5
33
5PKU
R246
4K7
FRE
S
ET#
DV
33
R2
8
9
10K
POCE0#
10K
R2
3
4
0.1U
C276
C266
0.1U
U0TX
1
2
EZJZ1V270RA
R
88
4K7
R
8
9
+5V
U
S
B_D-
U
S
B_D+
FLA
S
H MEMORY
B10
B10
I_17950_0
3
0.ep
s
07050
8