
Circuit Diagrams and PWB Layouts
10.
10-2-36
B, FPGA - DDR
19570_121_140603.eps
14-06-03
FPGA - DDR
B
B
2014-02-21
3
715RLPCB000000030
MV UHD HDMI20-420
C9
DQSL
DQSL
DQSU2
DQSU1
DMU
DML
RESET
WE
CS
CKE
CK
CK
CAS
ODT
RAS
ZQ
VREFCA
VREFDQ
NC
7
6
5
4
3
2
1
0
DQU
7
6
5
4
3
2
1
0
DQL
0
1
2
BA
VDD
VDDQ
VSS
VSSQ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
BC
AP
DQSL
DQSL
DQSU2
DQSU1
DMU
DML
RESET
WE
CS
CKE
CK
CK
CAS
ODT
RAS
ZQ
VREFCA
VREFDQ
NC
7
6
5
4
3
2
1
0
DQU
7
6
5
4
3
2
1
0
DQL
0
1
2
BA
VDD
VDDQ
VSS
VSSQ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
BC
AP
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
T7
L9
L1
J9
J1
H7
G2
H8
H3
F8
F2
F7
E3
G3
F3
C7
B7
A3
B8
A2
A7
C2
C8
C3
D7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
D3
E7
T2
L3
L2
K9
K7
J7
K3
K1
J3
M3
N8
M2
L8
M8
H1
M7
T3
N7
R7
L7
R3
T8
R2
R8
P2
P8
N2
P3
P7
N3
H5TQ1G63BFR-H9C
C7
B7
K1
M7
T3
U009B
+1V5-BEDDRA-FPGA
GND
1K
R172B
1%
+1V5-BEDDRA-FPGA
240
R176B
1%
50V
1nF
C122B
R173B
1K
1%
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
T7
L9
L1
J9
J1
H7
G2
H8
H3
F8
F2
F7
E3
G3
F3
C7
B7
A3
B8
A2
A7
C2
C8
C3
D7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
D3
E7
T2
L3
L2
K9
K7
J7
K3
K1
J3
M3
N8
M2
L8
M8
H1
M7
T3
N7
R7
L7
R3
T8
R2
R8
P2
P8
N2
P3
P7
N3
H5TQ1G63BFR-H9C
U012B
+1V5-BEDDRB-FPGA
GND
R174B
1K
1%
+1V5-BEDDRB-FPGA
R179B
240
1%
C123B
1nF
1%
1K
R175B
F032B
D009B
D010B
D011B
F033B
C029B
100nF
16V
C030B
100nF
C031B
100nF
16V
C032B
100nF
+1V5-BE
6.3V
10uF
C111B
16V
10nF
C114B
RES
C115B
10nF
16V
RES
16V
10nF
C116B
RES
C117B
10nF
16V
RES
+1V5-BEDDRA-FPGA
X007B
+1V5-BE
C112B
10uF
6.
3V
C118B
10nF
16V
RES
16V
10nF
C119B
RES
C120B
10nF
16V
RES
16V
10nF
C121B
RES
+1V5-BEDDRB-FPGA
X008B
100nF
C033B
C034B
100nF
100nF
C035B
C036B
100nF
100nF
C037B
C038B
100nF
C039B
100nF
100nF
C040B
C041B
100nF
100nF
C042B
C043B
100nF
100nF
C044B
+BEDDRA-VREF-FPGA
+BEDDRB-VREF-FPGA
D015B
D016B
D017B
D018B
R072B
100
1%
R073B
100
1%
I044B
I045B
GND
FPGA-BEDDRA-CLKB-P
FPGA-BEDDRA-CLKB-N
FPGA-BEDDRB-CLKB-N
FPGA-BEDDRB-CLKB-P
FPGA-BEDDRA-DQU0
FPGA-BEDDRA-DQU1
FPGA-BEDDRA-DQU2
FPGA-BEDDRA-DQU3
FPGA-BEDDRA-DQU4
FPGA-BEDDRA-DQU5
FPGA-BEDDRA-DQU6
FPGA-BEDDRA-DQU7
FPGA-BEDDRA-DQSU-N
FPGA-BEDDRA-DQSU-P
FPGA-BEDDRA-DQSL-P
FPGA-BEDDRA-DQSL-N
FPGA-BEDDRA-DQL0
FPGA-BEDDRA-DQL1
FPGA-BEDDRA-DQL2
FPGA-BEDDRA-DQL3
FPGA-BEDDRA-DQL4
FPGA-BEDDRA-DQL5
FPGA-BEDDRA-DQL6
FPGA-BEDDRA-DQL7
FPGA-BEDDRA-MA0
FPGA-BEDDRA-MA1
FPGA-BEDDRA-MA2
FPGA-BEDDRA-MA3
FPGA-BEDDRA-MA4
FPGA-BEDDRA-MA5
FPGA-BEDDRA-MA6
FPGA-BEDDRA-MA7
FPGA-BEDDRA-MA8
FPGA-BEDDRA-MA9
FPGA-BEDDRA-MA10
FPGA-BEDDRA-MA11
FPGA-BEDDRA-MA12
FPGA-BEDDRA-MA13
FPGA-BEDDRA-BA0
FPGA-BEDDRA-BA1
FPGA-BEDDRA-BA2
FPGA-BEDDRA-RASn
FPGA-BEDDRA-ODT
FPGA-BEDDRA-CASn
FPGA-BEDDRA-CLKB-P
FPGA-BEDDRA-CLKB-N
FPGA-BEDDRA-CKE
FPGA-BEDDRA-CSn
FPGA-BEDDRA-WEn
FPGA-BEDDRA-RSTn
FPGA-BEDDRA-DML
FPGA-BEDDRA-DMU
FPGA-BEDDRB-MA0
FPGA-BEDDRB-MA1
FPGA-BEDDRB-MA2
FPGA-BEDDRB-MA3
FPGA-BEDDRB-MA4
FPGA-BEDDRB-MA5
FPGA-BEDDRB-MA6
FPGA-BEDDRB-MA7
FPGA-BEDDRB-MA8
FPGA-BEDDRB-MA9
FPGA-BEDDRB-MA10
FPGA-BEDDRB-MA11
FPGA-BEDDRB-MA12
FPGA-BEDDRB-MA13
FPGA-BEDDRB-BA0
FPGA-BEDDRB-BA1
FPGA-BEDDRB-BA2
FPGA-BEDDRB-DML
FPGA-BEDDRB-DMU
FPGA-BEDDRB-RASn
FPGA-BEDDRB-ODT
FPGA-BEDDRB-CASn
FPGA-BEDDRB-CLKB-P
FPGA-BEDDRB-CLKB-N
FPGA-BEDDRB-CKE
FPGA-BEDDRB-CSn
FPGA-BEDDRB-WEn
FPGA-BEDDRB-RSTn
FPGA-BEDDRB-DQU3
FPGA-BEDDRB-DQU7
FPGA-BEDDRB-DQU2
FPGA-BEDDRB-DQU4
FPGA-BEDDRB-DQU0
FPGA-BEDDRB-DQU6
FPGA-BEDDRB-DQU1
FPGA-BEDDRB-DQSU-N
FPGA-BEDDRB-DQSU-P
FPGA-BEDDRB-DQSL-P
FPGA-BEDDRB-DQSL-N
FPGA-BEDDRB-DQL7
FPGA-BEDDRB-DQL1
FPGA-BEDDRB-DQL5
FPGA-BEDDRB-DQL0
FPGA-BEDDRB-DQL6
FPGA-BEDDRB-DQL3
FPGA-BEDDRB-DQL4
FPGA-BEDDRB-DQL2
FPGA-BEDDRB-DQU5