15
DP-IF8000
Pin No.
Pin name
I/O
Description
1
SCKISP
I
Serial clock signal input.
2
SS
I
SPI SLAVE select signal input.
3
HREQ
O
Host request select signal output.
4
SDO0
O
Serial data output.
5
SDO1
O
Serial data output.
6
SDO2
O
Serial data output.
7
SDO3
I
Serial data input.
8
VCCS
I
Power supply terminal.
9
GNDS
—
Ground terminal.
10
SDO4
I
Serial data input.
11
SDO5
I
Serial data input.
12
FST
I
Transmitter frame sync signal input.
13
FSR
I
Receiver frame sync signal input.
14
SCKT
I
Transmitter serial clock signal input.
15
SCKR
I
Receiver serial clock signal input.
16
HCKT
—
Not used (OPEN).
17
HCKR
—
Not used (OPEN).
18
VCCQL
I
Power supply terminal.
19
GNDQ
—
Ground terminal.
20
VCCQH
I
Power supply terminal.
21
PV12
—
Not used (OPEN).
22
PV11
—
Not used (OPEN).
23
PB15
—
Not used (OPEN).
24
PB14
—
Not used (OPEN).
25
VCCS
I
Power supply terminal.
26
GNDS
—
Ground terminal.
27
PD1
—
Not used (OPEN).
28
PD0
—
Not used (OPEN).
29
TIO0
I
Timer shumit triger signal input.
30
PD13
—
Not used (OPEN).
31
PD10
—
Not used (OPEN).
32
PB9
—
Not used (OPEN).
33
PB8
—
Not used (OPEN).
34
PB7
I
DSP control signal input.
35
PB6
I
DSP control signal input.
36
PB5
I
DSP control signal input.
37
PB4
I
DSP control signal input.
38
VCCH
I
Power supply terminal.
39
GNDH
—
Ground terminal.
40
PB3
I
DSP effect signal input.
41
PB2
I
DSP effect signal input.
42
PB1
I
DSP mute signal input.
43
PB0
O
No audio signal output.
44
RESET
I
Reset signal output.
45
VCCP
I
Power supply terminal.
46
PCAP
I
Capacitor connect terminal for PLL.
47
GNDP
—
Ground terminal.
48
SDI0-1
I
Serial data signal input.
• IC19 XCB56467PV150 (24 BIT AUDIO DIGITAL SIGNAL PROCESSOR) (1/3)
Содержание DP-IF8000
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