10.
Circuit Diagrams and PWB Layouts
SSB: PNX5100 - Power
C
V
SS
VDD_
3
V
3
_PER
V
SS
VDD_
3
V
3
_LVD
S
OUT
VDD_1V
8
_DDR
V
SS
VDD_
3
V
3
_LVD
S
IN
VDD_1V2_CORE
V
SS
V
SS
2C67-1 C2
D
E
2C66-
3
C2
2C61-2 B2
B
C
2
2C
8
0 D6
8
7
H
2C
8
4 D
8
1
2
2C
8
7 D9
2C
88
E9
2C66-2 C2
2C60-2 B1
11
2C6
3
-1 B
3
2C6
3
-2 B
3
2C6
3
-
3
E6
2C7
8
-4 D
3
10
I
PNX5100 : POWER
J
5C67 E
8
2C67-4 C2
2C6
8
-1 D1
2C6
8
-2 D2
2C66-4 C2
2C6
8
-4 D2
2C69-1 D2
2C69-2 D2
F
2C69-
3
D2
B
2C70-2 D
3
2C61-
3
B2
2C61-4 B2
2C62-1 B2
4
7
8
A
2C76 E
3
2C77 C9
2C7
8
-1 B1
IC
8
0 D7
IC
8
1 D7
IC
8
2 E7
2C79 D6
12
i
s
prohi
b
ited witho
u
t the written con
s
ent of the copyright
owner.
3
4
5
2C
83
F6
IC90 F9
3
10
9
2C
8
9 E9
4
2C60-
3
B1
2C60-4 B1
2C61-1 B2
9
2C7
8
-
3
B1
C
D
E
5C64 F6
5C65 F6
5C66 D
8
A
11
2C
8
1 B
3
2C
8
2 F6
2C67-2 C2
2C67-
3
C2
2C62-2 D6
2C62-
3
B2
2C62-4 E6
2C6
8
-
3
D2
2C64 B
3
2C65 B
3
2C66-1 C1
G
F
A
2C56 D1
2C57 D9
2C6
3
-4 B
3
6
2C60-1 B1
F
2C7
8
-2 B1
H
E
IC
83
E7
1
3
6
1
I
9
7
6
5
3
2
1
2C45 D1
2C55 D1
J
2C90 F9
2C91 F
8
2C92 F9
2C96 A2
2C97 A2
5C60 D6
2C5
8
F9
2C59 A1
IC
8
4 E7
2C95 A1
C
All right
s
re
s
erved. Reprod
u
ction in whole or in p
a
rt
s
4
3
5C61 D6
5C62 E6
12
8
2C
8
5 D9
2C
8
6 D9
2C69-4 D2
2C70-1 D
3
F
E
2C71 E2
6
5
2C70-
3
D
3
2C70-4 D
3
2C72 E2
2C7
3
E2
2C74 E2
2C75 E2
D
C
CC60 A
3
FC07 A2
IC
8
6 D9
IC
8
7 E9
IC
88
E9
5C6
8
E
8
5C69 E
8
5C70 F
8
7C00-10 A4
7C00-11 A7
7
IC
8
5 F7
5
D
B
2C94 F7
8
9
A
B
5C6
3
E6
IC
8
9 E9
1
3
G
2
1
IC
83
+
3
V
3
-PNX5100-LVD
S
-PLL
+
3
V
3
2C71
100n
+
3
V
3
1
8
100n
2C62-1
+1V2-PNX5100-DLL
IC
8
5
ROYAL PHILIP
S
ELECTRONIC
S
N.V. 200
8
200
8
-11-21
M
a
elegheer Ingrid
200
8
-10-10
3
A
3
S
UPPLY PNX5100
TV54
3
R2 LDIPNX
8
204 000
8
92
8
CHECK
DATE
NAME
2
S
UPER
S
.
CLA
SS
_NO
E
M
A
N
T
E
S
N
H
C
9
3
100n
1
3
0
+
3
V
3
2C74
+
3
V
3
-PNX5100-LVD
S
-PLL
1
8
+1V2-PNX5100-TRI-PLL2
+1V2-PNX5100
2C6
8
-1
100n
3
6
IC
88
6
2C60-
3
100n
2C67-
3
100n
3
2C62-
3
3
6
2C69-4
100n
45
100n
2C62-4
100n
4
100n
2C79
+1V2-PNX5100
1
8
3
0R
5C6
3
2
100n
2C7
8
-1
2C62-2
100n
2C70-
3
100n
3
6
2C6
8
-
3
100n
3
6
CC60
3
0R
5C69
27
100n
2C6
3
-2
+1V2-PNX5100-DLL
+
3
V
3
IC
8
6
10
u
2C97
100n
2C
8
6
10V
33
0
u
2C59
2C77
100n
2C66-1
1
8
2C61-2
100n
27
100n
+
3
V
3
-PNX5100-CLOCK
5C62
3
0R
2C61-4
100n
45
+1V2-PNX5100-TRI-PLL
3
45
100n
2C6
8
-4
+1V2-PNX5100
10
u
2C56
3
0R
5C64
IC
8
7
27
27
100n
2C67-2
100n
2C6
8
-2
+1V2-PNX5100-LVD
S
-PLL
IC
8
0
+1V2-PNX5100
100n
2C
8
2
+1V2-PNX5100-LVD
S
-PLL
100n
2C76
45
+
3
V
3
27
100n
2C6
3
-4
IC
8
1
100n
2C60-2
+1V2-PNX5100
+
3
V
3
-PNX5100-DDR-PLL0
+1V
8
-PNX5100
2C96
10
u
100n
2C7
3
2C45
220
u
16V
2C69-2
100n
27
+1V2-PNX5100-DLL
2C
8
9
100n
V
SS
_MCAB1
AC1
3
V
SS
_MCAB2
AB1
3
V
SS
A_TRI_PLL2
K4
V
SS
A_TRI_PLL
3
U4
V
SS
A_XTAL
AE12
V
SS
D_TRI_PLL1
J
3
V
SS
D_TRI_PLL2
K
3
V
SS
D_TRI_PLL
3
U
3
V
SS
_DDRPLL0
AD26
V
SS
_DDRPLL1
R22
V
SS
A_DLL0
L22
V
SS
A_DLL1
AB22
V
SS
A_DLL4
E22
V
SS
A_DLL7
U22
V
SS
A_LVD
S
1
A15
V
SS
A_LVD
S
2
C15
V
SS
A_LVD
S
IN
AB19
V
SS
A_TRI_PLL1
J4
VDDD_1V2_TRI_PLL1
H5
VDDD_1V2_TRI_PLL2
K5
VDDD_1V2_TRI_PLL
3
U5
VDD_1V2_DDRPLL0
AD25
VDD_1V2_DDRPLL1
N22
VDD_1V2_MCAB1
AB14
VDD_1V2_MCAB2
AC14
V
SS
A_DDRPLL1
T22
VDDA_1V2_TRI_PLL
3
T5
VDDA_1V2_UIP_PLL
AF12
VDDA_1V2_XTAL
AD1
3
VDDA_
3
V
3
_DDRPLL0
AE25
VDDA_
3
V
3
_LVD
S
1
B15
VDDA_
3
V
3
_LVD
S
2
D15
VDDA_
3
V
3
_LVD
S
IN
AB1
8
VDDA_
3
V
3
_
S
Y
S
_PLL
AD14
VDDA_1V2_DDRPLL1
P22
VDDA_1V2_DLL0
M22
VDDA_1V2_DLL1
AA22
VDDA_1V2_DLL4
F22
VDDA_1V2_DLL7
V22
VDDA_1V2_LVD
S
_PLL
E15
VDDA_1V2_TRI_PLL1
J5
VDDA_1V2_TRI_PLL2
L5
7C00-11
PNX5100E
Φ
S
UPPLY_2
VDDA_1V2_1_7_MCAB
AE14
1
8
+1V2-PNX5100-TRI-PLL1
10
u
2C57
100n
2C69-1
3
0R
5C67
2C7
8
-2
100n
27
2C60-1
100n
1
8
3
+1V2-PNX5100
2C6
3
-
3
100n
3
6
FC07
+1V2-PNX5100
100n
2C66-
3
2C75
100n
+1V2-PNX5100-CLOCK
+1V2-PNX5100
+
3
V
3
-PNX5100-LVD
S
-IN
2C
83
100n
+1V2-PNX5100
5C65
3
0R
AE26
AC2
AC
3
AC4
+
3
V
3
-PNX5100-CLOCK
R15
AC1
R2
3
R25
T11
T12
T1
3
T14
T15
V25
W2
3
AB5
P12
P1
3
P14
P15
P2
3
R11
R12
R1
3
R14
AB4
M1
3
M14
M15
M25
N11
N12
N1
3
N14
N15
P11
AB
3
F25
H2
3
J25
L11
L12
L1
3
L14
L15
M11
M12
A17
B2
A20
C2
C25
C
3
D
3
D4
E4
E5
AD1
AD2
AD24
AD
3
AE1
AE2
AF1
B1
A10
A1
3
AA25
V5
W5
AB6
AB7
D22
E6
E7
G5
M5
N5
A1
P16
R16
T16
AB15
AB17
D10
D1
3
D17
D20
AB20
AB16
AB
8
AB9
AC9
AD9
AE9
AF9
E16
L16
M16
N16
AA5
E
8
E9
F5
J22
K22
P5
R5
Y5
7C00-10
PNX5100E
S
UPPLY_1
Φ
45
2C66-4
100n
8
+1V2-PNX5100
2C6
3
-1
100n
1
10
u
2C95
5C6
8
3
0R
5C70
3
0R
IC90
2C94
100n
100n
2C
8
4
2C64
100n
27
2C
8
0
100n
8
100n
2C70-2
2C70-1
100n
1
2C61-
3
3
6
+1V2-PNX5100
100n
+
3
V
3
+1V2-PNX5100-TRI-PLL2
100n
2C72
45
IC
8
4
100n
2C70-4
IC
8
9
IC
8
2
3
0R
5C66
5
100n
2C67-4
4
3
0R
5C61
3
6
+1V2-PNX5100-CLOCK
100n
2C69-
3
2C
8
7
100n
2C
8
5
100n
100n
2C5
8
2C66-2
100n
27
+1V2-PNX5100
100n
2C
8
1
+1V2-PNX5100-DDR-PLL1
+1V2-PNX5100-TRI-PLL
3
+1V2-PNX5100
2C55
10
u
5
+1V2-PNX5100-DDR-PLL1
+1V2-PNX5100
100n
2C7
8
-4
4
100n
2C65
1
8
100n
2C61-1
+1V2-PNX5100-CLOCK
100n
2C
88
2C60-4
45
100n
2C91
100n
100n
2C92
+
3
V
3
-PNX5100-DDR-PLL0
+1V2-PNX5100
+1V2-PNX5100-TRI-PLL1
+
3
V
3
100n
2C7
8
-
3
3
6
+
3
V
3
-PNX5100-LVD
S
-IN
100n
2C90
1
8
5C60
3
0R
2C67-1
100n
S
EN
S
E+1V2-PNX5100
1
83
20_520_09072
8
.ep
s
09072
8