Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 81
LC8.1U LA
9.
Figure 9-3 Power Supply Architecture
Control Signal Functions:
•
STANDBY: Control of PSU to enable switched supplies,
active “low”, by Standby Controller WT61P7.
•
POWER_DOWN: Signal to 12V presence, active
“high”.
•
PWRDET: Signal to 3V3_SW presence for
MT5382 operation, ADC operation.
•
+12Vdisp_DETECT: Signal to 12Vdisp presence,
active “high”.
9.4
Front-End
All sets in this chassis use the “Alps TDQU” hybrid tuner. Refer
to diagram B2 for details.
For analog reception, the signal from the tuner is processed by
the MT5382 Main Processor via the M1971 SAW filter and
TDA9886 Analog IF-PLL demodulator.
For digital reception, the signal from the tuner is processed
directly by the MT5382 Main Processor.
In future ITV implementations, the MT5112 Channel Decoder
and ProIdiom MPEG2 decoder/encoder will be added (not
implemented in this chassis).
Refer to figure “Front-end implementation” for details.
Figure 9-4 Front-end implementation
DC-DC
NCP5422ADR26
BD25KA5WFP-E2
DC-DC
NCP5422ADR26
TPS74801DRCR
L78M05DCT
(provision)
+5Vtuner
+3V3STBY
+VDISP
+12V
+3V3-Standby
+12VAudio
+12VSND
-12VAudio
-12VSND
L5973D
(provision)
+12V (TCON)
+12Vbolt-on
+12Va
+24Vbolt-on
+24V
+5V_SW
+3V3_SW
+2V5
+1V1_SW
+1V8_SW
+1V2
STANDBY (from WT61P7)
POWER_DOWN (to MT5382 and WT61P7)
PWRDET (to MT5382)
+12Vdisp_DETECT (to MT5382) RES
H_17740_032.eps
230108
TDQU ALPS
TUNER
ANALOG
SAW
M1971
TDA9886
MT5382
S
4
5
17
12
1
1
2
11
10
9
5
4
ANALOG
IF
VIF1
VIF2
DIF1
DIF2
AC24
AB24
AC24
C24
D23
11
10
P25/24
TUNER SDA
TUNER SDA
TUNER CLK
TUNER CLK
CVBS
2nd SIF
4.5MHz
IF-AGC
H_17740_047.eps
250108
Содержание 32PFL3403D/85
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