Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 79
LC8.1U LA
9.
9.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
Index of this chapter:
9.1 Introduction
9.2 LCD Power Supply
9.3 DC/DC converters
9.4 Front-End
9.5 Video Processing
9.6 Audio Processing
9.7 HDMI
9.10 Abbreviation List
9.11 IC Data Sheets
Notes:
•
Only new circuits (circuits that are not published recently)
are described.
•
Figures can deviate slightly from the actual situation, due
to different set executions.
•
For a good understanding of the following circuit
descriptions, please use the Wiring, Block (chapter 6) and
Circuit Diagrams (chapter 7). Where necessary, you will
find a separate drawing for clarification.
9.1
Introduction
The LC8.1U chassis (development name “LC08SP”) is a newly
developed platform using a “Mediatek” chipset. It covers
screen sizes of 32" upto 52" with a new styling called “ME8”
and “MG8”. The MG8 is like the ME8 styling, however instead
of a transparent flare, it has a in-mould color flare. Also the
speakers are front firing as i.o. back-firing, and it comes w/o
tweeters. The back cover construction is 95% same as ME8.
Some key components are:
•
Main processor (MT5382): audio/video processing.
•
Motion estimation/compensation engine (MT8280) (in
some sets).
•
FPGA; I
2
C output to AmbiLight modules (in some sets).
•
HDMI demultiplexer (SIL9185) for driving 4 HDMI
connectors.
•
Standby controller (WT61P7) for overall power
management.
•
Analog IF-PLL demodulator (TDA9886).
•
Audio class-D amplifier (TDA8932).
9.1.1
Features
•
Hybrid NTSC/ATSC tuner.
•
3+1 HDMI v1.3, supporting CEC.
•
USB 2.0.
•
Digital Natural Motion (DNM) (in some sets).
•
Double Frame Rate (120 Hz) (in some sets).
•
2-sided AmbiLight (in some sets).
•
PSU directly drives the backlight units (no inverters
needed).
9.1.2
LC08SP Architecture Overview
For details of the chassis block diagrams refer to chapter
“Block diagrams, Test Point Overview, and Waveforms”. An
overview of the LC08SP architecture can be found below.
Figure 9-1 Architecture of LC08SP
TDA9886
MT5382
SAW Filter
NCP5422
+5V_SW
+3V3_SW
+1V8_SW
+1V1_SW
BD25KA5FP
+2V5
NCP5422
12V
Digital IF
SIF
VIF
Tuner
Alps TDQU
DDR2
DDR2
Flash
NVM
MT8280
DDR2
DDR2
Flash
Output up to
Quad LVDS
1920x1080p
100/120Hz
LVDS2
AV1 (YPbPr + LR)
AV2 (YPbPr + LR)
AV3 (CVBS/YC + LR)
SideAV (CVBS/YC + LR)
Headphone Output
SPDIF Output
HDMI1
HDMI2
HDMI3
HDMI4
USB
PC LR
MUX
PSU1
HP
Amp
Audio Amp
TDA8932
Speaker
Front
PSU2
UART (via Headphone)
uP
TPS74801
+1V2
JTAG
LVDS1
Output up to
Dual LVDS
1920x1080p
50/60Hz
LVDS3
L78M05CDT
+5Vtuner
Or
Ambi FPGA
EP2C5
JTAG
AMBI
OPTIONAL
Flash
H_17740_046.eps
240108
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