
15
In case [Bank change-over response register = 01H] (Initial value) (S-LINK V I/O unit connection address)
The first address of
S-LINK V
I/O units connected on the
S-LINK V
system main cable is
shown.
When each bit is “1,” the
S-LINK V
I/O unit having the set address is connected on the main
cable.
Note: When an
S-LINK V
? ? !
is “1.”
Computer I/O address
(hexadecimal)
S-LINK V
address
Port 1
Port 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
HL00 + 00B9
HL00 + 01B9
463
462
461
460
459
458
457
456
HL00 + 00BA
HL00 + 01BA
471
470
469
468
467
466
465
464
HL00 + 00BB
HL00 + 01BB
479
478
477
476
475
474
473
472
HL00 + 00BC
HL00 + 01BC
487
486
485
484
483
482
481
480
HL00 + 00BD
HL00 + 01BD
495
494
493
492
491
490
489
488
HL00 + 00BE
HL00 + 01BE
503
502
501
500
499
498
497
496
HL00 + 00BF
HL00 + 01BF
511
510
509
508
507
506
505
504
In case [Bank change-over response register = 02H] (Error 3 occurred address)
%
S-LINK V
I/O unit is indicated.
When each bit is “1,” the
S-LINK V
I/O unit connected to the address is disconnected or in er-
ror.
In case [Bank change-over response register = 03H] (Error 4 occurred address)
%
S-LINK V
I/O unit is indicated.
S-LINK V
I/O unit having the allocated
address.
In case [Bank change-over response register = 04H] (Error 5 occurred address)
%>
S-LINK V
I/O unit is indicated.
When each bit is “1,” output of
S-LINK V
output unit of the address is short-circuit, or I/O driving
power is interrupted.
In case [Bank change-over response register = 05H] (Occupied address)
The addresses allocated to the recognized
S-LINK V
units are indicated.
When each bit is “1,”
S-LINK V
I/O unit is connected to the address.
In case [Bank change-over response register = 06H] (I/O state)
Indicates whether the recognized address of the
S-LINK V
system is used as “Input” or “Output.”
The address is uesd as “Input” if the address corresponding to each bit is “1,” and as “Output” if
the address is “0.” (Unused address is “0.”)
Содержание SL-VVMES2
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