Panasonic SL-VVMES2, Инструкция по эксплуатации, Страница: 12 / 22

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It is used for checking if the output data is sent to S-LINK V output unit.
In case data is sent to the same address at an interval shorter than the S-LINK V system
response delay time, the data may not be transmitted. After the output data is written, if “1”
is written into HL00 + 004C or HL00 + 014C bit 0, and the next output data is written in after
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mission error can be avoided.
bit 1: “Error No. clear”
It clears the error No. in case the cause of error has been eliminated at “ 5) HL00 + 004A to
B
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HL00 + 014A to B: Error No. / Error state ” in “ 5. Assignment on Program ” and when
HL00 + 004A or HL00 + 014A bit 7 is “0.” If “1” is written into HL00 + 004C or HL00 + 014C
bit 1, HL00 + 004E or HL00 + 014E bit 1 turns to “1” after the error No. is cleared.
bit 2: “Default”
After “1” is written in, all the setting items are set to the initial conditions (Transmission
mode: A mode, I/O control numbers: 512) by reset (HL00 + 0054 to 5 or HL00 + 0154 to 5),
and the address information of the recognized units is cleared. If “1” is written into HL00 +
004C or HL00 + 014C bit 2, HL00 + 004E or HL00 + 014E bit 2 turns to “1” after the comple-
tion of the default setting. Then, execute the reset (HL00 + 0054 to 5 or HL00 + 0154 to 5).
bit 3: “System set”
It reads in the S-LINK V I/O unit connection state at that time. If “1” is written into HL00 +
004C or HL00 + 014C bit 3, HL00 + 004E or HL00 + 014E bit 3 turns to “1” after the comple-
tion of system setting.
bit 4: “Interruption indication”
In case interruption has occurred, HL00 + 004E or HL00 + 014E bit 4 turns to “1.” In order
to clear this, write “1” into HL00 + 004C or HL00 + 014C bit 4 to execute, and the clearance
is completed when HL00 + 004E or HL00 + 014E bit 4 turns to “0.” In case “0” is written into
HL00 + 004C or HL00 + 014C bit 4, it is ignored. After the clearance, in case HL00 + 004C
or HL00 + 014C bit 4 does not return to “0,” it will be cleared soon after the next interruption
occurs.
bit 5: “Busy indication”
When the Busy indicator lights up, such as during system setting, “1” is indicated in HL00 +
004E or HL00 + 014E bit 5. After the Busy state is over, it turns to “0.“
Even if written into HL00 + 004C or HL00 + 014C bit 5, this will be ignored.
bit 6: “On Hold indication”
In case the input hold is effective (HL00 + 0056 or HL00 + 0156 bit 0 is “1”), the current
state is indicated with Hold “1” or the state before Hold with “0.” When Hold cancel (HL00 +
0056 or HL00 + 0156 bit 0 is “0”) is set, it returns to “0.”
bit 7: “Command under execution indication”
After the receipt of each command of HL00 + 004C or HL00 + 014C bit 0 to 4, HL00 +
004E or HL00 + 014E bit 7 turns to “1” until the command completion. When the command
execution is completed, it turns to “0.” This bit allows you to check if a command has been
received.
6) HL00 + 004C to D, HL00 + 014C to D: Command execution request register
7) HL00 + 004E to F, HL00 + 014E to F: Command completion response register (read out only)
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tem set, Interruption, Busy, On Hold and command under execution.
bit
7 6 5 4 3 2 1 0
Command execution request register
(HL00 + 004C / HL00 + 014C)
Command completion response register
(HL00 + 004E / HL00 + 014E)
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Error No. clear request Error No. clear completion indication
Default request Default completion indication
System set request System set completion indication
Interruption request Interruption indication
- Busy indication
- On Hold indication
- Command under execution indication