Revision 01
June 12, 1997
Section 150-441-124
HiGain HLU-D41
PairGain Engineering - Plant Series
Page 5
4. Functional Operation
4.1
The HLU-D41 block diagram is shown in Figure 3.
Figure 3. HLU-D41 Block Diagram
The HLU-D41 uses one PairGain Technologies 2B1Q HDSL transceiver to establish a full duplex
784 kbps data link to the remote unit in the following sequence:
1
Multiplexed DS0 channels are extracted from the channel bank backplane. The number of
channels extracted is determined by the BAND option setting using the front panel Mode and
Choice Setup buttons, or the DS0 BANDWIDTH option using the Maintenance Terminal menus.
2
The DS0 channels optioned for A/B Robbed Bit Signaling (RBS) are properly formatted, then
the DS0 channels are passed to the DS1 formatter which builds a DS1 signal.
3
The formatter inserts DS1 framing information and generates the Idle Code (7F or FF) to
complete a 12 DS0 payload for the half-DS1 signal, then the half-DS1 signal is passed to the
HDSL framer.
4
The framer bit stuffs the half-DS1 signal into the HDSL payload envelope and adds the required
HDSL overhead.
5
The 784 kbps HDSL signal is encoded by the single pair transceiver into a 2B1Q signal.
6
The 2B1Q signal is coupled to the twisted pair line by a transformer in the line interface, which
allows the line interface to provide lightning and power cross protection.
7
The 784 kbps signal from the remote HDSL transceiver is received by the HDSL line interface.
8
The single pair transceiver does a two-wire to four-wire conversion of the signal using echo-
canceling technology, then the signal to be transmitted toward the channel bank is processed by
the HDSL framer which monitors its signal quality.
9
Detected errors are reported to the micro-processor, the payload is extracted, and up to 12 DS0
channels are transmitted to the channel bank, with the DS1 formatter locating the first DS0 in
