Orban OPTIMOD 8685, Руководство по эксплуатации

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OPTIMOD SURROUND PROCESSOR INSTALLATION
2-27
If the
AGC
gain reduction meter averages more gain reduction (lower on
the meter), re-adjust the S
URROUND
I
NPUT
R
EFERENCE
(VU or PPM) to a
higher level.
H) When finished, reset the 8685’s S
URROUND
E
XTERNAL
AGC control to Y
ES
, if re-
quired (e.g., if that was its setting prior to your setting the
S
URROUND
I
NPUT
R
EFERENCE
(VU or PPM) level).
Refer to step 2 on page 2-20.
8. Adjust the 2.0 input reference Level.
[Skip this step if you will not be using the 2.0 processing.]
Repeat step 7 on page 2-25, but use the
2.0 I
NPUT
R
EFERENCE
(VU OR PPM)
con-
trol. If you choose to calibrate using tone or program material, drive the 2.0
processing’s inputs. All four 2.0 processors share the same reference level.
9. Set the 2.0 output configuration.
[Skip this step if you will not be using the 2.0 processing.]
All four 2.0 processors share the same configuration and cannot be configured
independently.
A)
L
OCATE
to
I
NPUT
/
OUTPUT
> 2.0 O
UTPUT
(I
NPUT
/O
UTPUT
3).
B) Set the
2.0 O
UTPUT
S
YNC
to
I
NTERNAL
, IN 1-2
,
S
YNC
I
N
,
V
IDEO
S
YNC
, SDI
or any of
the 8685’s AES3id inputs.
•
I
NTERNAL
synchronizes output sample rate of the 2.0-connected hardware
output that carries the 2.0 processing to the 8685 internal crystal time base.
If there is no valid signal present on the chosen reference input, the 8685
uses internal sync until a valid signal appears.
•
S
YNC
I
N
synchronizes the output sample rate to AES3id, AES11id, or word
clock applied to the 8685’s S
YNC
I
NPUT
. It will overwrite the setting of the
8685’s
2.0 O
UTPUT
R
ATE
control.
•
IN 1-2
synchronizes the output sample rate to a signal appearing on AES3id
input 1-2.
•
V
IDEO
S
YNC
synchronizes the sample rate to a SMPTE 274M or SMPTE 296M-
compliant source applied to the 8685’s V
IDEO
S
YNC
I
NPUT
. It will overwrite
the setting of the 8685’s
2.0 O
UTPUT
R
ATE
control. This source is available
only if the optional HD-SDI module is installed.
•
SDI synchronizes the sample rate to a SMPTE 259M, 292M, or 424M-
compiant signal applied to the 8685’s HD-SDI input. This source is available
only if the optional HD-SDI module is installed.
When using Penteo in its loop-though mode when using HD-SDI input
and output (i.e. using the optional HD-SDI module’s AES3id inputs and
outputs to connect to the Penteo), it is unnecessary to lock the sample
rates appearing on the AES3id outputs to house sync because the AES3id