Orban OPTIMOD 8685, Руководство по эксплуатации

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OPTIMOD SURROUND PROCESSOR TECHNICAL DATA
6-11
The buffered output of IC201 is applied to IC204, a balanced output line
driver. This driver emulates a floating transformer. One side of its output can
be grounded without affecting its differential output level. IC204 and its right
channel counterpart IC205 are socketed for easy field replacement. All other
circuitry is surface-mounted.
The corresponding right channel circuitry is functionally identical to that just
described.
To understand this circuitry on the SDI module, compare the schematics on
pages 6-82 and 6-55.
3. Digital Sample Rate Converter (SRC) and Output Transmitter
Located on Input/output board
Output sample rate converter (SRC) chips IC304, 305, 306, 404, 405, 406 con-
vert the 8685’s 48 kHz system sample rate to any of the standard 32 kHz, 44.1
kHz, 48 kHz, 88.2 kHz, and 96 kHz rates for the 8685’s six AES3id outputs. The
sample rate converters drive digital audio interface transmitters IC301, 302,
3030, 401, 402, 403, which encode digital audio signals using the AES3id inter-
face format. These chips are surface-mounted and are not field-replaceable
without surface-mount rework equipment.
SDI Option:
The digital output transmitters for the AES3id outputs are U300AB U302B, and
U304B. The associated sample rate converters are U301A, U303A, and U305A.
The sample rate converters for channels 1/2, 3/4, 5/6, and 7/8 of the SDI output
are U402A, U402B, U403A, and U403B respectively.
DSP Circuit
The DSP circuit consists of nine Freescale (formerly Motorola) 250 MHz DSP56724
dual-core 24-bit fixed-point DSP chips that execute DSP software code to implement
digital signal processing algorithms. The none DSP chips, each operating at ap-
proximately 500 million instructions per second (MIPS), for a total of 4500 MIPS, pro-
vide the necessary signal processing. An internal sampling rate of 48 kHz is used.
System initialization normally occurs when power is first applied to the 8685 and can
occur abnormally if the 8685’s watchdog timer forces the SC520 to reboot. Upon ini-
tialization, the SC520 CPU downloads the DSP executable code stored in the flash
memory. The time between application of power and completion of DSP code
download is approximately 7 seconds. Once a DSP chip begins executing its program,
execution is continuous. The SC520 provides the DSP program with parameter data
(representing information like the settings of various processing controls), and ex-
tracts the front panel metering data from the DSP chips.