EVBUM2789
21
Table 18. COMMAND
Name: COMMAND
Address: 0Ah
Type: RW
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
DVSMODE
PWM
SLEEP_MODE
DISCHG
PGCLK
ENABLE
PGDVS
PGDCDC
Bit
Bit Description
PGDCDC
Power Good Enabling
0 = Disabled
1 = Enabled
PGDVS
Power Good Active On DVS
0 = Disabled
1 = Enabled
ENABLE
EN Pin Gating
0: Disabled
1: Enabled
PGCLK
Power Good CLK Enabling
0 = Disabled
1 = Enabled
DISCHG
Active discharge bit Enabling
0 = Discharge path disabled
1 = Discharge path enabled
SLEEP_MODE
Sleep mode
0 = Low Iq mode when EN low
1 = Force product in sleep mode
PWM
Operating mode selection
0 = Auto
1 = Forced PWM
DVSMODE
DVS transition mode selection
0 = Auto
1 = Forced PWM
Table 19. TIMING REGISTER
Name: TIME
Address: 0Bh
Type: RW
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
DELAY[1..0]
F_SPREAD[1..0]
DVS[1..0]
DBN_Time[1..0]
Bit
Bit Description
DBN_Time[1..0]
EN debounce time
00 = 1
−
2
m
s
01 = 1
−
2
m
s
10 = 2
−
3
m
s
11 = 3
−
4
m
s
DVS[1..0]
DVS Speed
00 = 10 mV step / 0.465
m
s
01 = 10 mV step / 0.930
m
s
10 = 10 mV step / 1.860
m
s
11 = 10 mV step / 3.720
m
s
F_SPREAD[1..0]
Spread Spectrum
00 = No Spread Spectrum
01 =
±
5 % spread spectrum
10 =
±
10 % spread spectrum
11 =
±
10 % spread spectrum
DELAY[1..0]
Delay applied upon enabling (ms)
00b = 0 ms – 11b = 6 ms (Steps of 2 ms)