EVBUM2789
16
REGISTERS DESCRIPTION
The tables below describe the I2C registers.
Registers / Bits Operations:
R
Read only register
W1C
Write to 1 to Clear
RW
Read and Write register
Reserved
Address is reserved and register / bit is not
physically designed
Spare
Address is reserved and register / bit is
physically designed
In
bold
default can be factory programmed upon request.
Table 8. INTERRUPT ACKNOWLEDGE REGISTER 1
Name: INTACK1
Address: 00h
Type: W1C
Default: 00000000b (00h)
Trigger: Dual Edge [D7..D0]
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
ACK_UVLO
ACK_UVP
ACK_OVP
Spare = 0
ACK_ISHORT ACK_IDCDCHS ACK_IDCDCLS
Bit
Bit Description
ACK_IDCDCLS
DC
−
DC Negative Over Current Sense Acknowledgement
0: Cleared
1: DC
−
DC Negative Over Current Event detected
ACK_IDCDCHS
DC
−
DC Over Current Sense Acknowledgement
0: Cleared
1: DC
−
DC Over Current Event detected
ACK_ISHORT
DC
−
DC Short
−
Circuit Protection Sense Acknowledgement
0: Cleared
1: DC
−
DC Short circuit protection detected
ACK_OVP
PV
IN
Overvoltage Protection Sense Acknowledgement
0: Cleared
1: OVP Event detected
ACK_UVP
PV
IN
Undervoltage Protection Sense Acknowledgement
0: Cleared
1: UVP Event detected
ACK_UVLO
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected