NCP1239
http://onsemi.com
35
Figure 58.
One clearly sees that the GTS signal does not react to the fugitive low FB Pin condition during startup
Figure 59.
Internal Go−To−Standby signal elaboration
+
−
Skip
+
0.43V
S
R
Q
Q
FB < V
pin7
=> Skip high
+
−
7
COMP1
COMP2
Stby_detect
GTS
pin1
100 ms timer (*)
(SS and timer block)
FB
15r
25r
100k
Skip
Adjust
REF5V
R1
R2
FB > 1.7 * V
pin7
=> Stby_detect RESET
(*) the 100 ms delay is programmed by the Pin 6 capacitor
Suppose our Flyback controller is built with a transformer
primary inductance of 250
H. To pass 120 W, we assume
that a peak current of 4.2 A was needed. Due to these
numbers, we can easily now when the GTS signal will be
asserted:
Lp, primary inductance = 250
H
= 85%
fsw, switching frequency = 65 kHz
Ip
+
2
@
Pout
@
Lp
@
fsw
Ǹ
+
4.2 A
Ip skip = 30% of Ip max = 1.26 A
The theoretical region at which the SMPS will enter
standby is: 1/2 * Lp * Ip
* fsw *
11 W. This number
can vary depending on the line level since the propagation
delay becomes a sensitive parameter, and on the efficiency
that is difficult to precisely predict in light load conditions.
The peak current at which the SMPS will leave standby is
48% of the peak current which means that a power of 28 W
is necessary to re−trigger the PFC.
