NCP1239
http://onsemi.com
34
315.4U
882.7U
1.450M
2.017M
2.585M
300.0M
200.0M
100.0M
0
25% of max Ip
Max peak
current
Figure 56.
The skip−cycle takes place at low peak currents which guaranties noise free operation
PFC Inhibition in Standby
The circuit detects a light load condition by permanently
monitoring the skip−cycle comparator activity: in normal
load condition this comparator keeps quiet. As soon as the
load strongly decreases, this comparator starts to toggle at a
low frequency rate: we are entering skip−cycle and the
opto−coupler operates in a digital manner, ON/OFF.
Figure 56 shows the way skip−cycle is detected. In skip
mode, the feedback voltage oscillates around V
pin7
(If no
voltage is applied to the Pin 7, a 430 mV voltage source
supplies a default value through a high impedance resistor).
In these conditions, the skip comparator (“COMP1”) that
turns on and off (to adjust the skip mode bunches of pulses),
sets the standby detection latch. A second comparator
(“COMP2”) compares the feedback voltage (FB or V
pin8
) to
1.7*V
pin7
.
As long as the load keeps light, FB does not exceed
1.7*V
pin7
(i.e., 0.74 V typical if no voltage is forced to
Pin 7). A timer counts down and if COMP2 keeps high for
100 ms (typically with 390 nF on Pin 6), the NCP1239
considers that the system runs in the standby mode. Pin 1
turns high, a 10 k
resistor tying the pin to V
CC
. If as shown
in Figure 39, Pin 1 directly drives a pnp transistor that is
connected between V
CC
and the PFC V
CC
, this switch turns
off in standby. As a result, this transistor stops feeding the
PFC V
CC
and ultimately shuts the PFC down.
As soon as FB exceeds 1.7*V
pin7
, the circuit leaves the
standby mode without any delay by forcing a 1 mA sinking
current source on Pin 1, that re−activates the pnp transistor
and then the PFC stage.
One can note that there is a 1/3 ratio between the actual
current setpoint and the feedback value FB. Therefore the
default thresholds for standby detection and normal mode
recovery (0.43 V, 0.74 V) actually corresponds to the
140 mV and 250 mV setpoints.
Figure 57.
A delay is inserted to avoid false tripping of the GTS signal
70%
