NCP1239
http://onsemi.com
18
Figure 37 depicts the V
CC
evolution during a proper startup sequence, showing the state of the error flag:
*This time is programmed by the Pin 6 capacitor. C
pin6
= 390 nF nearly sets the following intervals:
− Soft−Start Time (T
ss
):7.5 ms
− Jittering Period (T
jittering
): 10 ms
− Fault Detection Delay (T
delay
): 100 ms
More generally, the times approximately depend on C
pin6
as follows:
− T
ss
= 7.5 ms * C
pin6
/ 390 nF
− T
jittering
=10 ms * C
pin6
/ 390 nF
− T
delay
=100 ms * C
pin6
/ 390 nF
Figure 37.
7.5ms*
SS
Ip max
FB
Error
Flag
Timer
Full power
Skip level
VccON
VccOFF
Vcc
Latch−off phase level
Logic reset level
regulation
No error has
been confirmed
User
Powers up!
Feedback loop
reacts...
