NCP1060, NCV1060, NCP1063, NCV1063
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25
FB
COMP
R
COMP (up )
OTA
I
FB
V
COMP (REF )
V
REF
I
OTAlim
I
COMP
OTA out = 0 A
if FB = 0 V
Figure 45. FB Pin Connection
Design Procedure
The design of an SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices. Let us follow
the steps:
V
in
min = 90 Vac or 127 Vdc once rectified, assuming a low
bulk ripple
V
in
max = 265 Vac or 375 Vdc
V
out
= 12 V
P
out
= 5 W
Operating mode is CCM
η
= 0.8
1. The lateral MOSFET body−diode shall never be
forward biased, either during start−up (because of
a large leakage inductance) or in normal operation
as shown in Figure 46. This condition sets the
maximum voltage that can be reflected during toff.
As a result, the Flyback voltage which is reflected
on the drain at the switch opening cannot be larger
than the input voltage. When selecting
components, you thus must adopt a turn ratio
which adheres to the following equation:
N
@
ǒ
V
out
)
V
f
Ǔ
t
V
in,min
(eq. 2)
2. In our case, since we operate from a 127 V DC rail
while delivering 12 V, we can select a reflected
voltage of 120 V dc maximum. Therefore, the turn
ratio Np:Ns must be smaller than
V
reflect
V
out
)
V
f
+
120
12
)
0.5
+
9.6 or Np : Ns
t
9.6.
Here we choose N = 8 in this case. We will see later
on how it affects the calculation.
1.004M
1.011M
1.018M
1.025M
1.032M
−50.0
50.0
150
250
350
> 0 !!
Figure 46. The Drain−Source Wave Shall Always be Positive
