OKIDATA DOC-IT3000, Руководство по обслуживанию

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- (address range 8000 0000 to 87FF FFFF)
· Slow I/O bus cycle
- (address range 1000 0000 to 7FFF FFFF and 8800 0000 to EFFF FFFF)
The bus handshake control logic controls all the bus traffic and provides the request signals for
the memory interface, DMA controller, Doc-It Engine interface and DAA interface. If external
device bus cycles are active the IPC will be in the idle state, but will pass external ready signals to
the i960 or the HCC to terminate the bus cycle.
Page Memory Interface
The page memory interface (memory controller) generates all roll/column addresses for the on
board memory, contains CAS before RAS refresh logic, 16MHz/20MHz and 25MHz CAS timing
control logic and supports interleave/non-interleave page access mode.
The local address/data bus LAD[31:0] is selected as the memory data bus (MDE[31:0] and
MDO[31:0]) via the transceivers. Two banks of memory data (odd and even) are generated from
the local address/data bus via the control lines LDEG_N and LDOG_N. Single bank memory can
also be supported by cutting/setting the trace jumpers near U22. In this case, U27-30 would not
be populated and the MDE [31:0] would be the single data bus for the memory array with the trace
jumpers connected to tie the MDE and MDO busses together. The memory data lines can be
followed directly to the DRAMs and expansion memory connectors.
RAS and CAS lines are fed directly from the IPC, through series resistors and then directly to the
memory array. Page mode memory is utilized in this design. The RAS_# line indicates the
physical # of the memory bank. The RAS signal going low is the latch for the memory row
address.
The RAS signal is then held low for the duration of the cycle and the 4 even or odd CAS lines
select the column address within the appropriate page. The memory address lines (MA0:9) are
buffered from the IPC and sent directly to the memory array. The single memory write signal
XMWR_N is also buffered and split into MWRO_N and MWRE_N, which can be traced to the
memory array. The table below shows the mapping between the address source bits and the
memory address bits. The column address bits should increment accordingly in a burst DRAM
access.
Address Bit MA
9 MA
8 MA
7 MA
6 MA
5 MA
4 MA
3 MA
2 MA
1 MA
0
Row Address 21 19 18 17 16 15 14 13 12 11
Column Address
(Fast Mode) 22 10 9 8 7 6 5 4 3 20
Column Address
(Normal Mode) 20 10 9 8 7 6 5 4 3 2
The DRAM refresh is handled by the internal memory Controller on the IPC. The refresh cycle
should last for six or seven clock cycles (depending on the frequency of operation). The refresh