OKIDATA DOC-IT3000, Руководство по обслуживанию, Страница: 77 / 428

request has the highest priority of all requests for memory. The duration of refresh is
programmable.
In order to achieve zero wait state timing under a variety of system speeds, there are two sets of
CAS timing control logic (16 and 25MHz). One wait state is required for DRAM writes at 25MHz.
All reads at any system speed and writes below 25MHz can operate at 0 wait states, assuming
the 64 bit (odd/even, MDO[31:0] and MDE[31:0]) double banking path is chosen. The DRAM
configuration register is programmable to choose DRAM access in either a double or single bank
mode (as is the case where there is an odd number of memory banks..ex. 5 MB BANK 0/1
interleaved, BANK 2 non-interleaved, BANK 4/5 interleaved).
DMA Controller
The DMA Controller handles the data transfer between the IPC scan/print Controllers and DRAM.
Whenever scan or print data is present, the DMS Controller requests bus usage and after
arbitration and grant, will start to transfer data between the DRAM and the IPC. The DMA
Controller logic has two page buffers and has print erase and automatic termination capabilities.
Timer Logic
There are three programmable system timers within the IPC chip. Their functions are as follows:
· Timer 1
16 bits wide - this timer is reserved for DRAM refresh control. It will automatically load its data
from register and generate refresh request to the memory Controller whenever the count reaches
0.
· Timer 2
16 bits wide - user defined. It will automatically load data from register and issue an interrupt
request to the interrupt control logic in the IPC whenever the count reaches 0.
· Timer 3
8 bits wide - this timer is used for 10 uS and 1 mS timing generation, and its output is a square
wave. It will automatically load data from register and issue a request to the interrupt control logic
in the IPC whenever the count reaches 0.
Interrupt Control
The interrupt control logic generates interrupt signals for i80960KA and KB processor. All
interrupts are maskable via register.
INT0960,INT1960,INT2960 AND INT3960 are directly connected from the IPC to the processor.
Doc-It Engine Interface
The Doc-It Engine interface logic consists of scanner control, printer control and command
interface.
The scanner control receives serial data from the Doc-It Engine and sends 32 bit bussed data to
the DRAM via the on-board DMA logic. This logic has dual scan buffers and overrun protection.
The scanner control logic is also capable of inverting data bits, adding pad bits to an uncompleted
word, adding pack bits for an uncompleted byte, swapping nibbles in a byte, mirror image
processing, swapping bytes in a word, swapping bits in a byte and looping back data to the
printer.
The printer control receives 32 bit data from DRAM via on-board DMA logic and sends serial data
to the printer. The printer control logic is capable of supporting 300 and 400 dpi print functions,
including expand and shrink control, mirror image processing, reverse bit order in a word and
inverting data bits.
The command interface provides serial communication between the i960 and the Doc-It Engine
control panel. It receives 8 bit data from the i960 and sends a serial command to the Doc-It