FEAL60852A-02
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Semiconductor
ML60852A
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3.2.10.
–DREQ Signal interval during single transfer
In the ML60852A, it is possible to set the interval during the single transfer mode, that is, the interval
until –DREQ is asserted again after the completion of DMA transfer of the previous byte (or word).
This interval setting is made using the registers DMA0INTVL (address 11h) and DMA1INTVL
(address 13h).
One bit time is 84 ns (12 MHz, duration for 1 cycle).
Interval duration = (DREQ Enable time) + 84
×
n (ns)
3.2.11.
Setting packet ready during DMA transfer
When writing data into the FIFO of the ML60852A using DMA transfer (bulk-in transfer), there is no
need to set the packet ready bit of each end point from the local MCU side. When data with the
maximum packet size is written in the FIFO by the DMA controller, the ML60852A automatically sets
the packet ready bit. Therefore, there will be no need for the local MCU to access the ML60852A in the
middle of DMA transfer by setting the size of data to be transferred to the byte count register of the
DMA controller at the beginning of DMA transfer.
However, when the last packet to be transferred is a short packet (or a zero-length packet), it is
necessary for the local MCU to set the packet ready bit. In this case, it is possible to set the packet ready
bit by triggering the DMA transfer end interrupt that is issued by the DMA controller to the local MCU.
